LPC3131 datasheet(35/68 Pages) NXP

35 / 68 page

LPC3130_3131_1

Preliminary data sheet

Rev. 1 — 9 February 2009

35 of 68

NXP Semiconductors

LPC3130/3131

Low-cost, low-power ARM926EJ-S microcontrollers

6.29 System control registers

The System Control Registers (SysCReg) module provides a register interface for some

of the high-level settings in the system such as multiplexers and mode settings. This is an

auxiliary module included in this overview for the sake of completeness.

6.30 I2S0/1 interfaces

The I2S0/1 receive and I2S0/1 transmit modules have the following features:

• Audio interface compatible with the I2S standard.

• I2S0/1 receive supports master mode and slave mode.

• I2S0/1 transmit supports master mode.

• Supports LSB justiﬁed words of 16, 18, 20 and 24 bits.

• Supports a conﬁgurable number of bit clock periods per Word Select period (up to

128 bit clock periods).

• Supports DMA transfers.

• Transmit FIFO (I2S transmit) or receive FIFO (I2S receive) of 4 stereo samples.

• Supports single 16 bit transfers to/from the left or right FIFO.

• Supports single 24 bit transfers to/from the left or right FIFO.

• Supports 32-bit interleaved transfers, with the lower 16 bits representing the left audio

sample, and the higher 16 bits representing the right audio sample.

• Supports two 16-bit audio samples combined in a 32-bit word (2 left or 2 right

samples) to reduce busload.

• Provides maskable interrupts for audio status: FIFO underrun/overrun/full/

half_full/not empty for left and right channel separately.

LPC3131 Datasheet(PDF) 35 Page - NXP Semiconductors