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LPC3131 Datasheet(PDF) 7 Page - NXP Semiconductors |
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LPC3131 Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 68 page  LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 7 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers USB_VDDA12_PLL L1 SUP1 Supply - PS3 USB PLL supply USB_VDDA33_DRV M2 SUP3 Supply - PS3 USB Analog supply for driver USB_VDDA33 P1 SUP3 Supply - PS3 USB Analog supply for PHY USB_VSSA_TERM L3 Ground - CG1 USB Analog ground for clean reference for on chip termination resistors USB_GNDA N1 Ground - CG1 USB Analog ground USB_VSSA_REF K4 Ground - CG1 USB Analog ground for clean reference JTAG JTAGSEL N11 SUP3 DI I DIO1 JTAG selection. Controls output function of SCAN_TDO and ARM_TDO signals. TDI K9 SUP3 DI I DIO1 JTAG Data Input TRST_N P13 SUP3 DI I DIO1 JTAG Reset Input TCK M14 SUP3 DI I DIO1 JTAG Clock Input TMS P10 SUP3 DI I DIO1 JTAG Mode Select Input SCAN_TDO F10 SUP3 DO O/Z DIO1 JTAG TDO signal from scan TAP controller. Pin state is controlled by JTAGSEL. ARM_TDO E11 SUP3 DO O DIO1 JTAG TDO signal from ARM926 TAP controller. BUF_TRST_N F11 SUP3 DO O DIO1 Buffered TRST_N out signal. Used for connecting an on board TAP controller (FPGA, DSP, etc.). BUF_TCK D13 SUP3 DO O DIO1 Buffered TCK out signal. Used for connecting an on board TAP controller (FPGA, DSP, etc.). BUF_TMS D14 SUP3 DO O DIO1 Buffered TMS out signal. Used for connecting an on board TAP controller (FPGA, DSP, etc.). UART mUART_CTS_N[3][4] N13 SUP3 DI / GPIO I DIO1 UART Clear To Send (active LOW) mUART_RTS_N[3][4] P14 SUP3 DO / GPIO O DIO1 UART Ready To Send (active LOW) UART_RXD[3] P12 SUP3 DI / GPIO I DIO1 UART Serial Input UART_TXD[3] N12 SUP3 DO / GPIO O DIO1 UART Serial Output I2C master/slave interface I2C_SDA0 C10 SUP3 DIO I IICD I2C Data Line I2C_SCL0 D10 SUP3 DIO I IICC I2C Clock line I2C_SDA1[3] E12 SUP3 DIO O DIO1 I2C Data Line I2C_SCL1[3] E13 SUP3 DIO O DIO1 I2C Clock line Serial Peripheral Interface SPI_CS_OUT0[3] A7 SUP3 DO O DIO4 SPI Chip Select Output (Master) SPI_SCK[3] A8 SUP3 DIO I DIO4 SPI Clock Input (Slave) / Clock Output (Master) SPI_MISO[3] C8 SUP3 DIO I DIO4 SPI Data Input (Master) / Data Output (Slave) Table 4. Pin description Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins. Pin name BGA Ball Digital I/O level [1] Application function Pin state after reset Cell Type [2] Description |
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