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LPC3131 Datasheet(PDF) 1 Page - NXP Semiconductors |
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LPC3131 Datasheet(HTML) 1 Page - NXP Semiconductors |
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1 / 68 page  1. General description The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB 2.0 On-The-Go (OTG), up to 192 KB SRAM, NAND flash controller, flexible external bus interface, four channel 10-bit ADC, and a myriad of serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, and communication markets. To optimize system power consumption, the LPC3130/3131 have multiple power domains and a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling. 2. Features 2.1 Key features I CPU platform N 180 MHz, 32-bit ARM926EJ-S N 16 kB D-cache and 16 kB I-cache N Memory Management Unit (MMU) I Internal memory N 96 kB (LPC3130) or 192 kB (LPC3131) embedded SRAM I External memory interface N NAND flash controller with 8-bit ECC N 8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM I Communication and connectivity N High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY N Two I2S-bus interfaces N Integrated master/slave SPI N Two master/slave I2C-bus interfaces N Fast UART N Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA N Four-channel 10-bit ADC N Integrated 4/8/16-bit 6800/8080 compatible LCD interface I System functions N Dynamic clock gating and scaling N Multiple power domains N Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB N DMA controller N Four 32-bit timers N Watchdog timer LPC3130/3131 Low-cost, low-power ARM926EJ-S MCUs with high-speed USB 2.0 OTG, SD/MMC, and NAND flash controller Rev. 1 — 9 February 2009 Preliminary data sheet |
Similar Part No. - LPC3131 |
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