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LPC3131 Datasheet(PDF) 6 Page - NXP Semiconductors |
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LPC3131 Datasheet(HTML) 6 Page - NXP Semiconductors |
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6 / 68 page  LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 6 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers Row P 1 USB_VDDA33 2 USB_DP 3 mLCD_DB_14 4 mLCD_DB_13 5 mLCD_DB_7 6 mLCD_DB_3 7 mLCD_DB_5 8 mLCD_RS 9 mLCD_DB_1 10 TMS 11 I2SRX_WS0 12 UART_RXD 13 TRST_N 14 mUART_RTS_N - - - - Table 3. Pin allocation table …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol Table 4. Pin description Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins. Pin name BGA Ball Digital I/O level [1] Application function Pin state after reset Cell Type [2] Description Clock Generation Unit FFAST_IN A10 SUP1 AI - AIO2 12 MHz oscillator clock input FFAST_OUT B10 SUP1 AO AIO2 12 MHz oscillator clock output VDDA12 D11; E10 SUP1 Supply PS3 12 MHz oscillator/PLLs Analog supply VSSA12 E9 Ground - CG1 12 MHz oscillator/PLLs Analog ground RSTIN_N H14 SUP3 DI I DIO2 System Reset Input (active LOW) CLK_256FS_O H12 SUP3 DO O DIO1 Programmable clock output; fractionally derived from CLK1024FS_BASE clock domain. Generally used for Audio Codec master clock. CLOCK_OUT J4 SUP3 DO O DIO1 Programmable clock output; fractionally derived from SYS_BASE clock domain. SYSCLK_O[3] G13 SUP3 DO O DIO1 Programmable clock output. Output one of seven base/reference input clocks. No fractional divider. 10-bit ADC ADC10B_VDDA33 A13 SUP3 Supply - PS3 10-bit ADC Analog Supply ADC10B_GNDA A12 Ground - CG1 10-bit ADC Analog Ground ADC10B_GPA0 B14 SUP3 AI - AIO1 10-bit ADC Analog Input ADC10B_GPA1 A14 SUP3 AI - AIO1 10-bit ADC Analog Input ADC10B_GPA2 B13 SUP3 AI - AIO1 10-bit ADC Analog Input ADC10B_GPA3 C14 SUP3 AI - AIO1 10-bit ADC Analog Input USB HS 2.0 OTG USB_VBUS L2 SUP5 AI - AIO3 USB supply detection line USB_ID M1 SUP3 AI - AIO1 Indicates to the USB transceiver whether in device (USB_ID HIGH) or host (USB_ID LOW) mode (contains internal pull-up resistor) USB_RREF J5 SUP3 AIO - AIO1 USB Connection for external reference resistor (12 k Ω± 1 %) to analog ground supply USB_DP P2 SUP3 AIO - AIO1 USB D+ connection with integrated 45 Ω termination resistor USB_DM N2 SUP3 AIO - AIO1 USB D − connection with integrated 45 Ω termination resistor |
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