LPC3131 datasheet(49/68 Pages) NXP

49 / 68 page

LPC3130_3131_1

Preliminary data sheet

Rev. 1 — 9 February 2009

49 of 68

NXP Semiconductors

LPC3130/3131

Low-cost, low-power ARM926EJ-S microcontrollers

9.3 SDRAM controller

[1]

Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2]

All values valid for pads set to high slew rate. VDDE_IOA = VDDE_IOB = 1.8

± 0.15 V. VDDI = 1.2 ± 0.1 V.

[3]

foper = 1/TCLCL

Table 18.

Dynamic characteristics of SDR SDRAM memory interface

Tamb = −40 °C to +85 °C, unless otherwise speciﬁed; VDD(IO) = 1.8 V and 2.8 V (SUP8).[1][2]

Symbol

Parameter

Conditions

Min

Typical

Max

Unit

foper

operating frequency

[3] -

<tbd>

MHz

TCLCL

clock cycle time

<tbd>

tCLCX

clock LOW time

<tbd>

tCHCX

clock HIGH time

<tbd>

td(o)

output delay time

on pin EBI_CKE

3.5

on pins

EBI_NRAS_BLOUT,

EBI_NCAS_BLOUT,

EBI_NWE,

EBI_NDYCS

3.5

on pins EBI_DQM_1,

EBI_DQM_0_NOE

th(o)

output hold time

on pin EBI_CKE

0.2

3.5

on pins

EBI_NRAS_BLOUT,

EBI_NCAS_BLOUT,

EBI_NWE,

EBI_NDYCS

0.23

3.5

on pins EBI_DQM_1,

EBI_DQM_0_NOE

td(AV)

address valid delay

time

th(A)

address hold time

0.1

td(QV)

data output valid

delay time

th(Q)

data output hold time

tsu(D)

data input set-up

time

<tbd>

th(D)

data input hold time

<tbd>

tQZ

data output

high-impedance time

<TCLCL

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