LPC3131 datasheet(15/68 Pages) NXP

15 / 68 page

LPC3130_3131_1

Preliminary data sheet

Rev. 1 — 9 February 2009

15 of 68

NXP Semiconductors

LPC3130/3131

Low-cost, low-power ARM926EJ-S microcontrollers

6.3 JTAG

The Joint Test Action Group (JTAG) interface allows the incorporation of the

LPC3130/3131 in a JTAG scan chain.

This module has the following features:

• ARM926 debug access

• Boundary scan

6.4 NAND ﬂash controller

The NAND ﬂash controller is used as a dedicated interface to NAND ﬂash devices.

Figure 4 shows a block diagram of the NAND ﬂash controller module. The heart of the

module is formed by a controller block that controls the ﬂow of data from/to the AHB bus

through the NAND ﬂash controller block to/from the (external) NAND ﬂash. An error

correction encoder/decoder (ECC enc/dec) module allows for hardware error correction

for support of Multi-Level Cell (MLC) NAND ﬂash devices.

Before data is written from the buffer to the NAND ﬂash, optionally it is ﬁrst protected by

an error correction code generated by the ECC module. After data is read from the NAND

ﬂash, the error correction module corrects any errors.

This module has the following features:

• Dedicated NAND ﬂash interface with hardware controlled read and write accesses.

• Wear leveling support with 516 byte mode.

• Software controlled command and address transfers to support wide range of ﬂash

devices.

Fig 4.

Block diagram of the NAND ﬂash controller

002aae127

AHB MULTILAYER MATRIX

BUFFER

CONTROLLER

ECC

ENCODER/

DECODER

NAND INTERFACE

DMA transfer request

LPC3131 Datasheet(PDF) 15 Page - NXP Semiconductors