LPC3131 datasheet(40/68 Pages) NXP

40 / 68 page

LPC3130_3131_1

Preliminary data sheet

Rev. 1 — 9 February 2009

40 of 68

NXP Semiconductors

LPC3130/3131

Low-cost, low-power ARM926EJ-S microcontrollers

[1]

On pin ADC10B_GNDA.

[2]

Conditions: VSSA = 0 V on pin ADC10B_GNDA, VDD(ADC) = 3.3 V.

[3]

The ADC is monotonic, there are no missing codes.

[4]

The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 10.

[5]

The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 10.

[6]

The offset error (EO) is the absolute difference between the straight line which ﬁts the actual curve and the straight line which ﬁts the

ideal curve. See Figure 10.

[7]

The gain error (EG) is the relative difference in percent between the straight line ﬁtting the actual transfer curve after removing offset

error, and the straight line which ﬁts the ideal transfer curve. See Figure 10.

[8]

The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC

and the ideal transfer curve. See Figure 10.

[9]

See Figure 11.

Table 13.

ADC static characteristics

VDD(ADC) = 2.7 V to 3.6 V; Tamb = −40 °C to +85 °C unless otherwise speciﬁed; ADC frequency <tbd>.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIA

analog input voltage

0[1]

-VDD(ADC)

Cia

analog input capacitance

<tbd>

Nres(ADC)

ADC resolution

bit

differential linearity error

[2][3][4] --

±1

LSB

EL(adj)

integral non-linearity

[2][5] --

±1

LSB

offset error

[2][6] -

<tbd>

LSB

gain error

[2][7] -

<tbd>

absolute error

[2][8] -

<tbd>

LSB

Verr(O)

offset error voltage

−20

+20

Verr(FS)

full-scale error voltage

<tbd>

Rvsi

voltage source interface

resistance

[9] -

<tbd>

Ω

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