ADT7467ARQZ-R7 datasheet(25/77 Pages) ONSEMI

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ADT7467

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Generating SMBALERT Interrupts

From THERM Timer Events

The ADT7467 can generate SMBALERTs when a programma-

ble THERM timer limit has been exceeded. This allows the

system designer to ignore brief, infrequent THERM assertions

while capturing longer THERM timer events. Register 0x7A is

the THERM timer limit register. This 8-bit register allows a

limit from 0 sec (first THERM assertion) to 5.825 sec to be set

before an SMBALERT is generated. The THERM timer value is

compared with the contents of the THERM timer limit register.

If the THERM timer value exceeds the THERM timer limit,

the F4P bit (Bit 5) of Interrupt Status Register 2 is set and an

SMBALERT is generated. Note that the F4P bit (Bit 5) of Interrupt

Mask Register 2 (0x75) masks SMBALERT if this bit is set to 1;

however, the F4P bit of Interrupt Status Register 2 remains set if

the THERM timer limit is exceeded.

Figure 32 is a functional block diagram of the THERM timer,

limit, and associated circuitry. Writing a value of 0x00 to the

THERM timer limit register (0x7A) causes SMBALERT to be

generated upon the first THERM assertion. A THERM timer

limit value of 0x01 generates an SMBALERT once cumulative

THERM assertions exceed 45.52 ms.

22.76ms

45.52ms

91.04ms

182.08ms

364.16ms

728.32ms

1.457s

2.914s

OUT

RESET

LATCH

CLEARED

ON READ

F4P BIT (BIT 5)

INTERRUPT MASK REGISTER 2

(REG. 0x75)

1 = MASK

F4P BIT (BIT 5)

STATUS REGISTER 2

COMPARATOR

22.76ms

45.52ms

91.04ms

182.08ms

364.16ms

728.32ms

1.457s

2.914s

7 6 543 2 10

THERM LIMIT

(REG. 0x7A)

THERM TIMER

(REG. 0x79)

THERM TIMER CLEARED ON READ

SMBALERT

THERM

Figure 32. Functional Block Diagram of THERM Monitoring Circuitry

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