ADT7467ARQZ-R7 datasheet(4/77 Pages) ONSEMI

4 / 77 page

ADT7467

Rev. 3 | Page 4 of 77 | www.onsemi.com

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OPEN-DRAIN DIGITAL OUTPUTS, PWM1 to PWM3,

XTO

Current Sink, IOL

8.0

Output Low Voltage, VOL

0.4

IOUT = −8.0 mA, VCC = 3.3 V

High Level Output Current, IOH

0.1

1.0

μA

VOUT = VCC

OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)

Output Low Voltage, VOL

0.4

IOUT = −4.0 mA, VCC = 3.3 V

High Level Output Current, IOH

0.1

1.0

μA

VOUT = VCC

SMBus DIGITAL INPUTS (SCL, SDA)

Input High Voltage, VIH

2.0

Input Low Voltage, VIL

0.4

Hysteresis

500

DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)

Input High Voltage, VIH

2.0

5.5

Maximum input voltage

Input Low Voltage, VIL

0.8

−0.3

Minimum input voltage

Hysteresis

0.5

V p-p

DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+

Input High Voltage, VIH

0.75 × VCCP

Input Low Voltage, VIL

0.4

DIGITAL INPUT CURRENT

Input High Current, IIH

−1

μA

VIN = VCC

Input Low Current, IIL

μA

VIN = 0

Input Capacitance, CIN

SERIAL BUS TIMING

See Figure 2

Clock Frequency, fSCLK

400

kHz

Glitch Immunity, tSW

Bus Free Time, tBUF

4.7

μs

Start Setup Time, tSU; STA

4.7

μs

Start Hold Time, tHD; STA

4.0

μs

SCL Low Time, tLOW

4.7

μs

SCL High Time, tHIGH

4.0

μs

SCL, SDA Rise Time, tr

1000

SCL, SDA Fall Time, tf

300

μs

Data Setup Time, tSU; DAT

250

Data Hold Time, tHD; DAT

300

Detect Clock Low Timeout, tTIMEOUT

Can be optionally disabled

SCL

SDA

tBUF

tHD; STA

tHD; DAT

tSU; DAT

tLOW

tSU; STA

tHIGH

tHD; STA

tSU; STO

Figure 2. Serial Bus Timing Diagram

ADT7467ARQZ-R7 Datasheet(PDF) 4 Page - ON Semiconductor

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