ADT7467ARQZ-R7 datasheet(34/77 Pages) ONSEMI

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ADT7467

Rev. 3 | Page 34 of 77 | www.onsemi.com

MISCELLANEOUS FUNCTIONS

OPERATING FROM 3.3 V STANDBY

The ADT7467 has been specifically designed to operate from a

3.3 V STANDBY supply. In computers that support S3 and S5

states, the core voltage of the processor is lowered in these

states. If using the dynamic TMIN mode, lowering the core

voltage of the processor changes the CPU temperature and

changes the dynamics of the system under dynamic TMIN

control. Likewise, when monitoring THERM, the THERM

timer should be disabled during these states.

Dynamic TMIN Control Register 1 (0x36) <1> VCCPLO = 1

When the power is supplied from 3.3 V STANDBY and the VCCP

voltage drops below the VCCP low limit, the following occurs:

Status Bit 1 (VCCP) in Interrupt Status Register 1 is set.

SMBALERT is generated if enabled.

THERM monitoring is disabled. The THERM timer

should hold its value prior to the S3 or S5 state.

Dynamic TMIN control is disabled. This prevents TMIN from

being adjusted due to an S3 or S5 state.

The ADT7467 is prevented from shutting down.

Once the core voltage, VCCP, goes above the VCCP low limit,

everything is re-enabled and the system resumes normal

operation.

XNOR TREE TEST MODE

The ADT7467 includes an XNOR tree test mode. This mode is

useful for in-circuit test equipment at board-level testing. By

applying stimulus to the pins included in the XNOR tree, it is

possible to detect opens or shorts on the system board.

Figure 47 shows the signals that are exercised in the XNOR tree

test mode. The XNOR tree test is invoked by setting Bit 0

(XEN) of the XNOR tree test enable register (0x6F).

PWM1/XTO

PWM3

PWM2

TACH4

TACH3

TACH2

TACH1

Figure 47. XNOR Tree Test

POWER-ON DEFAULT

When the ADT7467 is powered up, it polls the VCCP input.

If VCCP stays below 0.75 V (the system CPU power rail is not

powered up), the ADT7467 assumes the functionality of the

default registers after the ADT7467 is addressed via any valid

SMBus transaction.

If VCC goes high (the system processor power rail is powered

up), a fail-safe timer begins to count down. If the ADT7467 is

not addressed by a valid SMBus transaction before the fail-safe

timeout (4.6 sec) lapses, the ADT7467 drives the fans to full

speed. If the ADT7467 is addressed by a valid SMBus

transaction after this point, the fans stop and the ADT7467

assumes its default settings and begins normal operation.

If VCCP goes high (the system processor power rail is powered

up), a fail-safe timer begins to count down. If the ADT7467 is

addressed by a valid SMBus transaction before the fail-safe

timeout (4.6 sec) lapses, the ADT7467 operates normally,

assuming the functionality of all default registers. See the flow

chart in Figure 48.

ADT7467 IS POWERED UP

HAS THE ADT7467 BEEN

ACCESSED BY A VALID

SMBUS TRANSACTION?

IS VCCP ABOVE 0.75V?

CHECK VCCP

START FAIL-SAFE TIMER

HAS THE ADT7467 BEEN

ACCESSED BY A VALID

SMBUS TRANSACTION?

FAIL-SAFE TIMER ELAPSES

AFTER THE FAIL-SAFE TIMEOUT

HAS THE ADT7467 BEEN

ACCESSED BY A VALID

SMBUS TRANSACTION?

START UP THE

ADT7467 NORMALLY

RUN THE FANS TO FULL SPEED

HAS THE ADT7467 BEEN

ACCESSED BY A VALID

SMBUS TRANSACTION?

SWITCH OFF FANS

Figure 48. Power-On Flowchart

ADT7467ARQZ-R7 Datasheet(PDF) 34 Page - ON Semiconductor

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