ADT7490ARQZ-R7 datasheet(48/75 Pages) ONSEMI

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ADT7490

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Table 20. ADT7490 Registers

Addr

Lock-

able

De-

fault

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Desc

R/W

0x94

R/W

PECI0

Temp.

Offset

0x00

Yes

0x95

R/W

PECI1

Temp.

Offset

0x00

Yes

0x96

R/W

PECI2

Temp.

Offset

0x00

Yes

0x97

R/W

PECI3

Temp.

Offset

0x00

Yes

−

0x41

−

0x74

OOL

R2T

R1T

+5VIN

VCC

VCCP

+2.5VIN/

THERM

Table 21. Register 0x10 — Configuration Register 6 (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W (Note 1)

Description

[0]

SLOW

Remote 1

R/W

When this bit is set, fan smoothing times are multiplied x4 for Remote 1 temperature channel

(as defined in Register 0x62).

[1]

SLOW

Local

R/W

When this bit is set, fan smoothing times are multiplied x4 for local temperature channel

(as defined in Register 0x63).

[2]

SLOW

Remote 2

R/W

When this bit is set, fan smoothing times are multiplied x4 for Remote 2 temperature channel

(as defined in Register 0x63).

[3]

Res

N/A

Reserved.

[4]

Res

N/A

Reserved.

[5]

Res

N/A

Reserved.

[6]

VCCP Low

R/W

VCCP Low = 1. When the power is supplied from 3.3 V STANDBY and the core voltage

(VCCP) drops below its VCCP low limit value (Register 0x46), the following occurs:

Status Bit 1 in Status Register 1 is set.

SMBALERT is generated, if enabled.

PROCHOT monitoring is disabled.

Everything is re−enabled once VCCP increases above the VCCP low limit.

When VCCP increases above the low limit:

PROCHOT monitoring is enabled.

Fans return to their programmed state after a spin−up cycle.

[7]

ExtraSlow

R/W

When this bit is set, all fan smoothing times are increased by a further 39.2%

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this

Table 22. Register 0x11 — Configuration Register 7 (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W (Note 1)

Description

[0]

THERMHys

R/W

THERM hysteresis is enabled by default. Setting this bit to 1 disables THERM hysteresis.

[1]

FSPD

R/W

When set to 1, this bit runs all fans at maximum speed as programmed in the maximum PWM

duty cycle registers (0x38 to 0x3A). Power−on default = 0. This bit is not locked at any time.

[2]

Vx1

R/W

BIOS should set this bit to 1 when the ADT7490 is configured to measure current from an

Analog Devices ADOPT VRM controller and to measure the CPU core voltage. This bit

allows monitoring software to display CPU watts usage. (Lockable.)

[3]

FSPDIS

R/W

Logic 1 disables fan spin−up for two TACH pulses. Instead, the PWM outputs go high for the

entire fan spin−up timeout selected.

[4]

TODIS

R/W

When this bit is set to 1, the SMBus timeout feature is disabled. In this state, if at any point

during an SMBus transaction involving the ADT7490 activity ceases for more than 35 ms, the

ADT7490 assumes the bus is locked and releases the bus. This allows the ADT7490 to be

used with SMBus controllers that cannot handle SMBus timeouts. (Lockable.)

[7:5]

RES

N/A

Reserved. Do not write to these bits.

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this

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