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ADT7490ARQZ-R7 Datasheet(PDF) 64 Page - ON Semiconductor |
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ADT7490ARQZ-R7 Datasheet(HTML) 64 Page - ON Semiconductor |
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64 / 75 page  ADT7490 http://onsemi.com 64 Table 65. Register 0x75 — Interrupt Mask Register 2 (Power−On Default = 0x00) Bit No. Mnemonic R/W Description [0] +12 VIN R/W When Pin 21 is configured as a +12 VIN input, +12 VIN = 1 masks SMBALERT for out−of−limit conditions on the +12 VIN channel. [1] OOL R/W OOL = 1 masks SMBALERT assertions when the OOL status bit is set. Note that the OOL mask bit is independent of the individual mask bits in Interrupt Mask Register 3 (0x82). Therefore, if the intention is to mask SMBALERT assertions for any of the Interrupt Status Register 4 bits, OOL must also be masked. [2] FAN1 R/W FAN1 = 1 masks SMBALERT for a Fan 1 fault. [3] FAN2 R/W FAN2 = 1 masks SMBALERT for a Fan 2 fault. [4] FAN3 R/W FAN3 = 1 masks SMBALERT for a Fan 3 fault. [5] Fan4/ THERM R/W If Pin 14 is configured as TACH4, Fan4/ THERM = 1 masks SMBALERT for a Fan 4 fault. If Pin 14 is configured as THERM, Fan4/ THERM = 1 masks SMBALERT for an exceeded THERM timer limit. [6] D1 FAULT R/W D1 = 1 masks SMBALERT for a diode open or short on a Remote 1 channel. [7] D2 FAULT R/W D2 = 1 masks SMBALERT for a diode open or short on a Remote 2 channel. Table 66. Register 0x76 — Extended Resolution Register 1 (Power−On Default = 0x00) (Note 1) Bit No. Mnemonic R/W Description [1:0] +2.5 VIN Read−only +2.5 VIN LSBs. Holds the 2 LSBs of the 10−bit +2.5 VIN measurement. [3:2] VCCP Read−only VCCP LSBs. Holds the 2 LSBs of the 10−bit VCCP measurement. [5:4] VCC Read−only VCC LSBs. Holds the 2 LSBs of the 10−bit VCC measurement. [7:6] +5 VIN Read−only +5 VIN LSBs. Holds the 2 LSBs of the 10−bit +5 VIN measurement. 1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read. Table 67. Register 0x77 — Extended Resolution Register 2 (Power−On Default = 0x00) (Note 1) Bit No. Mnemonic R/W Description [1:0] +12 VIN Read−only +12 VIN LSBs. Holds the 2 LSBs of the 10−bit +12 VIN measurement. [3:2] TDM1 Read−only Remote 1 temperature LSBs. Holds the 2 LSBs of the 10−bit Remote 1 temperature measurement. [5:4] LTMP Read−only Local temperature LSBs. Holds the 2 LSBs of the 10−bit local temperature measurement. [7:6] TDM2 Read−only Remote 2 temperature LSBs. Holds the 2 LSBs of the 10−bit Remote 2 temperature measurement. 1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read. |
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