ADT7490ARQZ-R7 datasheet(51/75 Pages) ONSEMI

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Table 32. Register 0x36 — PECI Configuration Register 1 (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W (Note 1)

Description

[2:0]

AVG[2:0]

R/W

PECI Smoothing Interval. These bits set the duration over which smoothing is carried out on

the PECI data read. Note that the PECI smoothing interval is equal to the PECI register

update interval. The smoothing interval is calculated using the following formula:

Smooth Interval = #reads x (tBIT x 67 x #CPU + tIDLE)

where:

#reads is the number of readings defined below.

tBIT is the negotiated bit rate.

67 is the number of bits in each PECI reading.

#CPU is the number of CPUs providing PECI data (1 to 4).

tIDLE = 14 ms, the delay between consecutive reads.

Bit Code

Number of PECI Readings

000

001

010

011

100

101

110

111

2048

4096

8192

16384

32768

65536

Reserved

[3]

DOM0

R/W

CPU Domain Count information. Set to 0 indicates that CPU 1 associated with the PECI0

reading has a single domain (default). Set to 1 indicates that the system CPU 1 contains two

domains.

[4]

REPLACE

R/W

If this bit is set to 0, it indicates that the ADT7490 is operating in standard mode. If this bit is

set to 1, the Remote 1 Temperature register (Register 0x25) is overwritten by PECI0

information (Register 0x33) and vice versa. Note that in this mode, all associated user

programmable limit and fan control registers are also swapped and should be programmed in

the appropriate PECI or absolute temperature format.

[7:5]

RES

Reserved.

1. These registers become read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to

these registers fail.

Table 33. Maximum PWM Duty Cycle (Power−On Default = 0xFF) (Note 1)

R/W (Note 2)

Description

0x38

R/W

Maximum duty cycle for PWM1 output, default = 100% (0xFF).

0x39

R/W

Maximum duty cycle for PWM2 output, default = 100% (0xFF).

0x3A

R/W

Maximum duty cycle for PWM3 output, default = 100% (0xFF).

1. These registers set the maximum PWM duty cycle of the PWM output.

2. These registers become read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to

these registers fail.

Table 34. PECI TMIN Register (Power−On Default = 0xE0, Value = −32)

R/W (Note 1)

Description

0x3B

R/W

PECI TMIN. When the PECI measurement exceeds PECI TMIN, the appropriate fans run at

PWMMIN and increase according to the automatic fan speed control slope.

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set. Any further attempts to write to this register

have no effect.

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