ADT7490ARQZ-R7 datasheet(24/75 Pages) ONSEMI

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ADT7490

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Table 16. Interrupt Status and Interrupt Mask Register Address and Bit Assignments

Interrupt

Status

Interrupt

Mask

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x41

0x74

OOL

R2T

R1T

+5 VIN

VCC

VCCP

+2.5 VIN/THERM

0x42

0x75

D2 FAULT

D1 FAULT

FAN4/THERM

FAN3

FAN2

FAN1

OOL

+12 VIN

0x43

0x82

OOL

RES

OVT

COM

DATA

PECI0

0x81

0x83

VTT

IMON

PECI3

PECI2

PECI1

RES

SMBALERT Interrupt Behavior

The ADT7490 can be polled for status, or an SMBALERT

interrupt can be generated for out−of−limit conditions. It is

important to note how the SMBALERT output and status

bits behave when writing interrupt handler software.

Figure 30. SMBALERT and Status Bit Behavior

STICKY

STATUS BIT

HIGH LIMIT

TEMPERATURE

CLEARED ON READ

(TEMP BELOW LIMIT)

TEMP BACK IN LIMIT

(STATUS BIT STAYS SET)

SMBALERT

Figure 30 shows how the SMBALERT output and sticky

status bits behave. Once a limit is exceeded, the

corresponding status bit is set to 1. The status bit remains set

until the error condition subsides and the status register is

read. The status bits are referred to as sticky, because they

remain set until read by software. This ensures that an

out−of−limit event cannot be missed if software is polling

the device periodically.

Note that the SMBALERT output remains low for the

entire duration that a reading is out of limit and until the

status register has been read. This has implications on how

software handles the interrupt.

Handling SMBALERT Interrupts

To prevent the system from being tied up servicing

interrupts, it is recommend to handle the SMBALERT

interrupt as follows:

1. Detect the SMBALERT assertion.

2. Enter the interrupt handler.

3. Read the status registers to identify the interrupt

source.

4. Mask the interrupt source by setting the

appropriate mask bit in the interrupt mask registers

(0x74, 0x75, 0x82, and 0x83).

5. Take the appropriate action for a given interrupt

source.

6. Exit the interrupt handler.

7. Periodically poll the status registers. If the

interrupt status bit has cleared, reset the

corresponding interrupt mask bit to 0. This causes

the SMBALERT output and status bits to behave

as shown in Figure 31.

Masking Interrupt Sources

The interrupt mask registers allow individual interrupt

sources to be masked out to prevent SMBALERT interrupts.

Note that masking an interrupt source prevents only the

SMBALERT output from being asserted; the appropriate

status bit is set normally (see Figure 31). Full details of the

status and mask registers associated with each measurement

channel are detailed in Table 16 and Table 20.

Figure 31. How Masking the Interrupt Source Affects

SMBALERT Output

STICKY

STATUS BIT

HIGH LIMIT

TEMPERATURE

CLEARED ON READ

(TEMP BELOW LIMIT)

TEMP BACK IN LIMIT

(STATUS BIT STAYS SET)

INTERRUPT

MASK BIT SET

SMBALERT

INTERRUPT MASK BIT

CLEARED

(SMBALERT REARMED)

Enabling the SMBALERT Interrupt Output

The SMBALERT interrupt function is disabled by

default. Pin 10 or Pin 14 can be reconfigured as an

SMBALERT output to signal out−of−limit conditions.

Table 17. Configuring Pin 10 as SMBALERT Output

Bit Setting

Configuration Register 3

(Register 0x78), Bit 0

[1] Pin 10 = SMBALERT

[0] Pin 10 = PWM2 (default)

Assigning THERM Functionality to a Pin

Pin 14 on the ADT7490 has three possible functions:

SMBALERT, THERM, and TACH4. The user chooses the

required functionality by setting Bit 0 and Bit 1 of

Configuration Register 4 at Address 0x7D.

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