ADT7490ARQZ-R7 datasheet(42/75 Pages) ONSEMI

42 / 75 page

ADT7490

http://onsemi.com

Bit 5 (MIN1) = 0, PWM1 is off (0% PWM duty cycle) when

the temperature is below TMIN − THYST.

Bit 5 (MIN1) = 1, PWM1 runs at PWM1 minimum duty

cycle below TMIN − THYST.

Configuration Register 6 (Register 0x10)

Bit 0 (SLOW) = 1, slows the ramp rate for PWM changes

associated with the Remote 1 temperature channel by 4.

Bit 1 (SLOW) = 1, slows the ramp rate for PWM changes

associated with the local temperature channel by 4.

Bit 2 (SLOW) = 1, slows the ramp rate for PWM changes

associated with the Remote 2 temperature channel by 4.

Bit 7 (ExtraSlow) = 1, slows the ramp rate for all fans by a

factor of 39.2%.

The following sections list the ramp−up times when the

SLOW bit is set for each temperature monitoring channel.

Enhanced Acoustics Register 1 (Register 0x62)

Bits [2:0] ACOU, selects the ramp rate for PWM outputs

associated with the Remote Temperature 1 input.

000 = 37.5 sec

001 = 18.8 sec

010 = 12.5 sec

011 = 7.5 sec

100 = 4.7 sec

101 = 3.1 sec

110 = 1.6 sec

111 = 0.8 sec

Enhanced Acoustics Register 2 (Register 0x63)

Bits [2:0] ACOU3, selects the ramp rate for PWM outputs

associated with the local temperature channel.

000 = 37.5 sec

001 = 18.8 sec

010 = 12.5 sec

011 = 7.5 sec

100 = 4.7 sec

101 = 3.1 sec

110 = 1.6 sec

111 = 0.8 sec

[6:4] ACOU2, selects the ramp rate for PWM outputs

associated with the Remote Temperature 2 input.

000 = 37.5 sec

001 = 18.8 sec

010 = 12.5 sec

011 = 7.5 sec

100 = 4.7 sec

101 = 3.1 sec

110 = 1.6 sec

111 = 0.8 sec

When Bit 7 of Configuration Register 6 (0x10) = 1, the

preceding ramp rates change to

000 = 52.2 sec

001 = 26.1 sec

010 = 17.4 sec

011 = 10.4 sec

100 = 6.5 sec

101 = 4.4 sec

110 = 2.2 sec

111 = 1.1 sec

Setting the appropriate SLOW Bit 2, Bit 1, or Bit 0 of

Configuration Register 6 (0x10) slows the ramp rate

further by a factor of 4.

Programming the GPIOs

The ADT7490 has two dedicated GPIOs (Pin 5 and

Pin 6).The direction (input or output) and polarity (active

high or active low) of the GPIOs is set in the GPIO

Configuration Register (0x80). Bit 2 and Bit 3 of Register

0x80 also reflect the state of the GPIO pins when configured

as inputs and assert the GPIO pins when configured as

outputs.

XNOR Tree Test Mode

The ADT7490 includes an XNOR tree test mode. This

mode is useful for in−circuit test equipment at board−level

testing. By applying stimulus to the pins included in the

XNOR tree, it is possible to detect opens, or shorts, on the

system board.

The XNOR tree test is invoked by setting Bit 0 (XEN) of

the XNOR Tree Test Enable register (Register 0x6F).

Figure 61 shows the signals that are exercised in the

XNOR tree test mode.

Figure 61. XNOR Tree Test

PWM1/XTO

PWM3

PWM2

TACH4

TACH3

TACH2

TACH1

ADT7490ARQZ-R7 Datasheet(PDF) 42 Page - ON Semiconductor

ADT7490ARQZ-R7 Datasheet(HTML) 42 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

Datasheet Download

Link URL