ADT7490ARQZ-R7 datasheet(13/75 Pages) ONSEMI

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ADT7490

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4. The master sends a command code.

5. The slave asserts ACK on SDA.

6. The master asserts a stop condition on SDA and

the transaction ends.

For the ADT7490, the send byte protocol is used to write

a register address to RAM for a subsequent single−byte read

from the same address. This operation is illustrated in

Figure 21.

Figure 21. Setting a Register Address for

Subsequent Read

SLAVE

ADDRESS

SA P

ADDRESS

15 6

If the master is required to read data from the register

immediately after setting up the address, it can assert a repeat

start condition immediately after the final ACK and carry

out a single−byte read without asserting an intermediate stop

condition.

Write Byte

In this operation, the master device sends a command byte

and one data byte to the slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7−bit slave address followed

by the write bit (low).

3. The addressed slave device asserts ACK on SDA.

4. The master sends a command code.

5. The slave asserts ACK on SDA.

6. The master sends a data byte.

7. The slave asserts ACK on SDA.

8. The master asserts a stop condition on SDA, and

the transaction ends.

The byte write operation is illustrated in Figure 22.

Figure 22. Single Byte Write to a Register

SLAVE

ADDRESS W A

DATA

A P

ADDRESS

7 8

Read Operations

The ADT7490 uses the following SMBus read protocols.

Receive Byte

This operation is useful when repeatedly reading a single

this operation, the master device receives a single byte from

a slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7−bit slave address followed

by the read bit (high).

3. The addressed slave device asserts ACK on SDA.

4. The master receives a data byte.

5. The master asserts NO ACK on SDA.

6. The master asserts a stop condition on SDA, and

the transaction ends.

In the ADT7490, the receive byte protocol is used to read

a single byte of data from a register whose address has

previously been set by a send byte or write byte operation.

This operation is illustrated in Figure 23.

Figure 23. Single−Byte Read from a Register

SLAVE

ADDRESS

DATA

SA P

15 6

Alert Response Address

Alert response address (ARA) is a feature of SMBus

devices that allows an interrupting device to identify itself

to the host when multiple devices exist on the same bus.

The SMBALERT output can be used as either an interrupt

output or an SMBALERT. One or more outputs can be

connected to a common SMBALERT line connected to the

master. If a device’s SMBALERT line goes low, the

following events occur:

1. SMBALERT is pulled low.

2. The master initiates a read operation and sends the

alert response address (ARA = 0001 100). This is

a general call address that must not be used as a

specific device address.

3. The device whose SMBALERT output is low

responds to the alert response address, and the

master reads its device address. The address of the

device is now known and can be interrogated in

the usual way.

4. If more than one device’s SMBALERT output is

low, the one with the lowest device address has

priority in accordance with normal SMBus

arbitration.

5. Once the ADT7490 has responded to the alert

response address, the master must read the status

registers, and the SMBALERT is cleared only if

the error condition is gone.

SMBus Timeout

The ADT7490 includes an SMBus timeout feature. If

there is no SMBus activity for 35 ms, the ADT7490 assumes

the bus is locked and releases the bus. This prevents the

device from locking or holding the SMBus expecting data.

Some SMBus controllers cannot work with the SMBus

timeout feature, so it can be disabled.

Configuration Register 7 (Register 0x11)

Bit 4 (TODIS) = 0, SMBus timeout enabled (default)

Bit 4 (TODIS) = 1, SMBus timeout disabled

Voltage Measurement Input

The ADT7490 has six external voltage measurement

channels. It can also measure its own supply voltage, VCC.

Pin 20 to Pin 23 can measure 5.0 V, 12 V, and 2.5 V

supplies, and the processor core voltage VCCP (0 V to 3.0 V

input). The 2.5 V input can be used to monitor a chipset

supply voltage in computer systems. The VCC supply

voltage measurement is carried out through the VCC pin

(Pin 4). Pin 8 measures the VTT voltage of the processor and

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