ADT7490ARQZ-R7 datasheet(23/75 Pages) ONSEMI

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ADT7490

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THERM Timer Limit Register

16−Bit Limits

The fan TACH measurements are 16−bit results. The fan

TACH limits are also 16 bits, consisting of a high byte and

low byte. Only high limits exist for fan TACHs because fans

running under speed or stalled are normally the only

conditions of interest. Because the fan TACH period is

actually being measured, exceeding the limit indicates a

slow or stalled fan.

Fan Limit Registers

Out−of−Limit Comparisons

Once all limits have been programmed, the ADT7490 can

be enabled for monitoring. The ADT7490 measures all

voltage and temperature measurements in round−robin

format and sets the appropriate status bit to indicate

out−of−limit conditions. TACH measurements are not part

of this round−robin cycle. Comparisons are done differently

depending on whether the measured value is being

compared to a high or low limit.

High Limit > Comparison Performed

Low Limit

≤ Comparison Performed

Voltage and temperature channels use a window

comparator for error detecting and, therefore, have high and

low limits. Fan speed measurements use only a low limit.

Analog Monitoring Cycle Time

The analog monitoring cycle begins when a 1 is written to

the start bit (Bit 0) of Configuration Register 1 (0x40). The

ADC measures each analog input in turn and, as each

measurement is completed, the result is automatically stored

in the appropriate value register. This round−robin

monitoring cycle continues unless disabled by writing a 0 to

Bit 0 of Configuration Register 1.

As the ADC is normally left to free−run in this manner, the

time taken to monitor all the analog inputs is normally not

of interest, because the most recently measured value of any

input can be read out at any time. For applications where the

monitoring cycle time is important, it can easily be

calculated.

The total number of channels measured consists of

• Six dedicated supply voltage inputs

• Supply voltage (VCC pin)

• Local temperature

• Two remote temperatures

As mentioned previously, the ADC performs round−robin

conversions and takes 11 ms for each voltage measurement,

12 ms for a local temperature reading, and 39 ms for each

remote temperature reading. The total monitoring cycle time

for averaged voltage and temperature monitoring is,

therefore, nominally

11) ) 12 ) (2

39) + 167 ms

(eq. 5)

Fan TACH measurements and PECI thermal measurements

are made in parallel and are not synchronized with the analog

measurements in any way.

Interrupt Status Registers

The results of limit comparisons are stored in Interrupt

Status Register 1 to Interrupt Status Register 4. The status

measurement and limit comparison on that channel. If a

measurement is within limits, the corresponding interrupt

status register bit is cleared to 0. If the measurement is out of

limit, the corresponding interrupt status register bit is set to 1.

The state of the various measurement channels can be

polled by reading the interrupt status registers over the serial

bus. In Bit 7 (OOL) of Interrupt Status Register 1 (0x41), a

Logic 1 indicates an out−of−limit event has been flagged in

Interrupt Status Register 2. This means the user also needs to

read Interrupt Status Register 2. There is a similar OOL bit in

Interrupt Status Register 2 and Interrupt Status Register 3,

indicating an out−of−limit event in the next status register.

Alternatively, Pin 10 or Pin 14 can be configured as an

SMBALERT output. This hard interrupt automatically

notifies the system supervisor of an out−of−limit condition.

Reading the interrupt status registers clears the appropriate

status bit as long as the error condition that caused the

interrupt has cleared. Interrupt status register bits are sticky.

Whenever an interrupt status bit is set, indicating an

out−of−limitcondition, it remains set even if the event that

caused it has gone away (until read).

The only way to clear the interrupt status bit is to read the

interrupt status register after the event has gone away.

Interrupt status mask registers allow individual interrupt

sources to be masked from causing an SMBALERT on the

dedicated alert pin. However, if one of these masked

interrupt sources goes out of limit, its associated interrupt

status bit is set in the interrupt status registers.

Full details of the Interrupt Status and Interrupt Mask

registers associated with each measurement channels are

detailed in the Table 16 and in the full register map in the

ADT7490ARQZ-R7 Datasheet(PDF) 23 Page - ON Semiconductor

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