ADT7490ARQZ-R7 datasheet(63/75 Pages) ONSEMI

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ADT7490

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Table 63. Register 0x73 — Configuration Register 2 (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W (Note 1)

Description

FanPresDT

R/W

When FanPresDT = 1, the state of Bits [3:1] of this register reflects the presence of a 4−wire

fan on the appropriate TACH channel.

Fan1Detect

Read−only

Fan1Detect = 1 indicates that a 4−wire fan is connected to the PWM1 input.

Fan2Detect

Read−only

Fan2Detect = 1 indicates that a 4−wire fan is connected to the PWM2 input.

Fan3Detect

Read−only

Fan3Detect = 1 indicates that a 4−wire fan is connected to the PWM3 input.

AVG

R/W

AVG = 1 indicates that averaging on the temperature and voltage measurements is turned

off. This allows measurements on each channel to be made much faster (x16).

ATTN

R/W

ATTN = 1 indicates that the ADT7490 removes the attenuators from the +2.5 VIN, VCCP,

+5 VIN, and +12 VIN inputs. These inputs can be used for other functions such as connecting

up external sensors. It is also possible to remove attenuators from individual channels using

Bits [7:4] of Configuration Register 4 (0x7D).

CONV

R/W

CONV = 1 indicates that the ADT7490 is put into a single−channel ADC conversion mode. In

this mode, the ADT7490 can be made to read continuously from one input only, for example,

Remote 1 temperature. The appropriate ADC channel is selected by writing to Bits [7:4] of

TACH1 minimum high byte register (0x55).

When CONV = 1, Bits [7:4], Register 0x55

Bit Code

ADC Channel Selected

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

+2.5 VIN

VCCP

VCC

+5 VIN

+12 VIN

Remote 1 temperature

Local temperature

Remote 2 temperature

VTT

IMON

Shutdown

R/W

When the shutdown bit is set to 1, the ADT7490 goes into shutdown mode.

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register

have no effect.

Table 64. Register 0x74 — Interrupt Mask Register 1 (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W

Description

[0]

+2.5 VIN/

THERM

R/W

+2.5 VIN/THERM = 1 masks SMBALERT for out−of−limit conditions on the +2.5 VIN/THERM

timer channel.

[1]

VCCP

R/W

VCCP = 1 masks SMBALERT for out−of−limit conditions on the VCCP channel.

[2]

VCC

R/W

VCC = 1 masks SMBALERT for out−of−limit conditions on the VCC channel.

[3]

+5 VIN

R/W

+5 VIN = 1 masks SMBALERT for out−of−limit conditions on the +5 VIN channel.

[4]

R1T

R/W

R1T = 1 masks SMBALERT for out−of−limit conditions on the Remote 1 temperature channel.

[5]

R/W

LT = 1 masks SMBALERT for out−of−limit conditions on the local temperature channel.

[6]

R2T

R/W

R2T = 1 masks SMBALERT for out−of−limit conditions on the Remote 2 temperature channel.

[7]

OOL

R/W

OOL = 1 masks SMBALERT assertions when the OOL status bit is set.

Note that the OOL mask bit is independent of the individual mask bits associated with

Interrupt Status Register 2. Therefore, if the intention is to mask SMBALERT assertions for

any of the Interrupt Status Register 2 bits, OOL must also be masked.

ADT7490ARQZ-R7 Datasheet(PDF) 63 Page - ON Semiconductor

ADT7490ARQZ-R7 Datasheet(HTML) 63 Page - ON Semiconductor

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