ADT7490ARQZ-R7 datasheet(68/75 Pages) ONSEMI

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ADT7490

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Table 73. Register 0x7D — Configuration Register 4 (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W (Note 1)

Description

[1:0]

Pin 14 Func

R/W

These bits set the functionality of Pin 14.

00 = TACH4 (default)

01 = THERM

10 = SMBALERT

11 = Reserved

[2]

THERM

Disable

R/W

THERM Disable = 0 enables THERM overtemperature output assuming THERM is correctly

configured (0x78, 0x7C, and 0x7D).

THERM Disable = 1 disables THERM overtemperature output on all channels. THERM can

also be disabled on any channel by:

Writing −64°C to the appropriate THERM temperature limit in Offset 64 mode.

Writing −128°C to the appropriate THERM temperature limit in twos complement mode.

[3]

Max/Full on

THERM

R/W

Max/Full on THERM = 0 indicates that fans go to 100% when THERM temperature limit is

exceeded.

Max/Full on THERM = 1 indicates that fans go to maximum speed (0x38, 0x39, 0x3A) when

THERM temperature limit is exceeded.

[4]

BpAtt

+2.5 VIN

R/W

Bypass +2.5VIN attenuator. When set, the measurement scale for this channel changes from

0 V (0x00) to 2.25 V (0xFF).

[5]

BpAtt VCCP

R/W

Bypass VCCP attenuator. When set, the measurement scale for this channel changes from

0 V (0x00) to 2.25 V (0xFF).

[6]

BpAtt

+5 VIN

R/W

Bypass +5 VIN attenuator. When set, the measurement scale for this channel changes from

0 V (0x00) to 2.25 V (0xFF).

[7]

BpAtt

+12 VIN

R/W

Bypass +12 VIN attenuator. When set, the measurement scale for this channel changes from

0 V (0x00) to 2.25 V (0xFF).

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register

have no effect.

Table 74. Register 0x7E — Manufacturer’s Test Register 1 (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W (Note 1)

Description

[7:0]

Reserved

Read−only

Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and

should not be written to under normal operation.

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register

have no effect.

Table 75. Register 0x7F — Manufacturer’s Test Register 2 (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W (Note 1)

Description

[7:0]

Reserved

Read−only

Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and

should not be written to under normal operation.

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register

have no effect.

Table 76. Register 0x80 — GPIO Configuration Register (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W

Description

[1:0]

RES

Reserved

Reserved.

[2]

GPIO2

R/W

If GPIO2 is set to input, this register reflects the state of the pin. If GPIO2 is configured as an

output, writing to this register asserts the output high or low depending on the polarity.

[3]

GPIO1

R/W

If GPIO1 is set to input, this register reflects the state of the pin. If GPIO1 is configured as an

output, writing to this register asserts the output high or low depending on the polarity.

[4]

GPIO2 POL

R/W

GPIO2 polarity bit. Set to 0 for active low. Set to 1 for active high.

[5]

GPIO1 POL

R/W

GPIO1 polarity bit. Set to 0 for active low. Set to 1 for active high.

[6]

GPIO2 DIR

R/W

GPIO2 direction bit. Set to 1 for GPIO1 to act as an input, set to 0 for GPIO2 to act as an output.

[7]

GPIO1 DIR

R/W

GPIO1 direction bit. Set to 1 for GPIO1 to act as an input, set to 0 for GPIO1 to act as an output.

ADT7490ARQZ-R7 Datasheet(PDF) 68 Page - ON Semiconductor

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