ADT7490ARQZ-R7 datasheet(73/75 Pages) ONSEMI

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Table 85. Register 0x90 — Dynamic TMIN Control Register 3 (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W (Note 1)

Description

[2:0]

RES

Reserved

[5:3]

CYP

R/W

3−Bit PECI Temperature Cycle Value. These three bits define the delay time between making

subsequent TMIN adjustments in the control loop for the PECI temperature channels in terms

of number of monitoring cycles. The system has associated thermal time constants that need

to be found to optimize the response of fans and the control loop.

Bit Code

Decrease Cycle

Increase Cycle

000

001

010

011

100

101

110

111

8 cycles (1 sec)

16 cycles (2 sec)

32 cycles (4 sec)

64 cycles (8 sec)

128 cycles (16 sec)

256 cycles (32 sec)

512 cycles (64 sec)

1024 cycles (128 sec)

16 cycles (2 sec)

32 cycles (4 sec)

64 cycles (8 sec)

128 cycles (16 sec)

256 cycles (32 sec)

512 cycles (64 sec)

1024 cycles (128 sec)

2048 cycles (256 sec)

[6]

PHTP

R/W

PHTR1 = 1 copies the PECI0 current reading to the PECI operating point register if THERM

is asserted. The operating point contains the temperature at which THERM is asserted,

allowing the system to run as quietly as possible without affecting system performance.

PHTR1 = 0 ignores any THERM assertions on the THERM pin. The PECI operating point

[7]

PECI

R/W

PECI = 1 enables dynamic TMIN control on the PECI temperature channel. The chosen TMIN

value is dynamically adjusted based on the current temperature, operating point, and high

and low limits for this zone.

PECI = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted and the

channel behaves as described in the Automatic Fan Control Overview section.

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this

Table 86. Register 0x94 — PECI0 Temperature Offset (Power−On Default = 0x00)

Bit No.

R/W (Note 1)

Description

[7:0]

R/W

Allows a temperature offset to be automatically applied to the PECI0 channel measurements. The

programmable offset range is from −63°C to +127°C with 1°C resolution.

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register

have no effect.

Table 87. Register 0x95 — PECI1 Temperature Offset (Power−On Default = 0x00)

Bit No.

R/W (Note 1)

Description

[7:0]

R/W

Allows a temperature offset to be automatically applied to the PECI1 channel measurements. The

programmable offset range is from −63°C to +127°C with 1°C resolution.

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register

have no effect.

Table 88. Register 0x96 — PECI2 Temperature Offset (Power−On Default = 0x00)

Bit No.

R/W (Note 1)

Description

[7:0]

R/W

Allows a temperature offset to be automatically applied to the PECI2 channel measurements. The

programmable offset range is from −63°C to +127°C with 1°C resolution.

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register

have no effect.

Table 89. Register 0x97 — PECI3 Temperature Offset (Power−On Default = 0x00)

Bit No.

R/W (Note 1)

Description

[7:0]

R/W

Allows a temperature offset to be automatically applied to the PECI3 channel measurements. The

programmable offset range is from −63°C to +127°C with 1°C resolution.

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register

have no effect.

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