ADT7490ARQZ-R7 datasheet(69/75 Pages) ONSEMI

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Table 77. Register 0x81 — Interrupt Status Register 4 (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W

Description

[2:0]

RES

Read−only

Reserved.

[3]

PECI1

Read−only

A Logic 1 indicates that the PECI high or low limit has been exceeded by the PECI value

from PECI Client Address 0x31. This bit is cleared on a read of the status register only if the

error condition has subsided.

[4]

PECI2

Read−only

A Logic 1 indicates that the PECI high or low limit has been exceeded by the PECI value

from PECI Client Address 0x32. This bit is cleared on a read of the status register only if the

error condition has subsided.

[5]

PECI3

Read−only

A Logic 1 indicates that the PECI high or low limit has been exceeded by the PECI value

from PECI Client Address 0x33. This bit is cleared on a read of the status register only if the

error condition has subsided.

[6]

IMON

Read−only

A Logic 1 indicates that the IMON high or low limit has been exceeded. This bit is cleared on a

read of the status register only if the error condition has subsided.

[7]

VTT

Read−only

A Logic 1 indicates that the VTT high or low limit has been exceeded. This bit is cleared on a

read of the status register only if the error condition has subsided.

Table 78. Register 0x82 — Interrupt Mask Register 3 (Power−On Default = 0x00) (Note 1)

Bit No.

Mnemonic

R/W

Description

[0]

PECI0

R/W

A Logic 1 masks SMBALERT assertions for out−of−limit conditions on PECI0.

[1]

DATA

R/W

A Logic 1 masks SMBALERT assertions for PECI data errors.

[2]

COMM

R/W

A Logic 1 masks SMBALERT assertions for PECI communications errors.

[3]

OVT

R/W

OVT = 1 masks SMBALERT for overtemperature THERM conditions.

[6:4]

RES

R/W

Reserved.

[7]

OOL

R/W

OOL = 1 masks SMBALERT assertions when the OOL status bit is set.

Note that the OOL mask bit is independent of the individual mask bits of Interrupt Mask Re-

gister 4 (0x83). Therefore, if the intention is to mask SMBALERT assertions for any of the

Interrupt Status Register 4 bits, OOL must also be masked.

1. If the mask bits in Register 0x82 are set, it is also necessary to set the OOL mask bit in Register 0x75 to ensure the SMBALERT output

is not asserted.

Table 79. Register 0x83 — Interrupt Mask Register 4 (Power−On Default = 0x00) (Note 1)

Bit No.

Mnemonic

R/W

Description

[2:0]

RES

R/W

Reserved.

[3]

PECI1

R/W

A Logic 1 masks ALERT assertions for out−of−limit conditions on PECI1.

[4]

PECI2

R/W

A Logic 1 masks ALERT assertions for out−of−limit conditions on PECI2.

[5]

PECI3

R/W

A Logic 1 masks ALERT assertions for out−of−limit conditions on PECI3.

[6]

IMON

R/W

A Logic 1 masks ALERT assertions for out−of−limit conditions on IMON.

[7]

VTT

R/W

A Logic 1 masks ALERT assertions for out−of−limit conditions on VTT.

1. If the mask bits in Register 0x83 are set, it is also necessary to set the OOL mask bit in Register 0x82 to ensure the SMBALERT output

is not asserted.

Table 80. VTT, IMON Limit Registers

R/W (Note 1)

Description

Power−On Default

0x84

R/W

VTT low limit

0x00

0x85

R/W

IMON low limit

0x00

0x86

R/W

VTT high limit

0xFF

0x87

R/W

IMON high limit

0xFF

1. These registers becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to

these registers fail.

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