ADT7490ARQZ-R7 datasheet(62/75 Pages) ONSEMI

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Table 58. Register 0x6E — Remote 2 and PECI Temperature/TMIN Hysteresis (Power−On Default = 0x44)

Bit No.

(Note 1)

Mnemonic

R/W

(Note 2)

Description

[3:0]

HYSP

R/W

PECI temperature hysteresis. 0°C to 15°C of hysteresis can be applied to the PECI AFC

control loops.

[7:4]

HYSR2

R/W

Remote 2 temperature hysteresis. 0°C to 15°C of hysteresis can be applied to the local

temperature AFC control loops.

1. Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that

channel falls below its TMIN value, the fan remains running at PWMMIN duty cycle until the temperature = TMIN − hysteresis. Up to 15°C of

hysteresis can be assigned to any temperature channel. The hysteresis value chosen also applies to that temperature channel, if its THERM

limit is exceeded. The PWM output being controlled goes to 100%, if the THERM limit is exceeded and remains at 100% until the temperature

drops below THERM − hysteresis. For acoustic reasons, it is recommended that the hysteresis value not be programmed less than 4°C.

Setting the hysteresis value lower than 4°C causes the fan to switch on and off regularly when the temperature is close to TMIN.

2. These registers become read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to these

registers have no effect.

Table 59. Register 0x6F — XNOR Tree Test Enable (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W (Note 1)

Description

[0]

XEN

R/W

If the XEN bit is set to 1, the device enters the XNOR tree test mode. Clearing the bit

removes the device from the XNOR tree test mode.

[7:1]

RES

R/W

Unused/reserved. Do not write to these bits.

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register

have no effect.

Table 60. Register 0x70 — Remote 1 Temperature Offset (Power−On Default = 0x00)

Bit No.

R/W (Note 1)

Description

[7:0]

R/W

Allows a temperature offset to be automatically applied to the Remote 1 temperature channel measurement.

Bit 1 of Configuration Register 5 (0x7C) determines the range and resolution of this register.

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register

have no effect.

Table 61. Register 0x71 — Local Temperature Offset (Power−On Default = 0x00)

Bit No.

R/W (Note 1)

Description

[7:0]

R/W

Allows a temperature offset to be automatically applied to the local temperature measurement. Bit 1 of

Configuration Register 5 (0x7C) determines the range and resolution of this register.

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register

have no effect.

Table 62. Register 0x72 — Remote 2 Temperature Offset (Power−On Default = 0x00)

Bit No.

R/W (Note 1)

Description

[7:0]

R/W

Allows a temperature offset to be automatically applied to the Remote 2 temperature channel measurement.

Bit 1 of Configuration Register 5 (0x7C) determines the range and resolution of this register.

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register

have no effect.

ADT7490ARQZ-R7 Datasheet(PDF) 62 Page - ON Semiconductor

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