MAC7200 datasheet(635/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

557

29.5.2.3

I2C Control Register

Offset 0x0002

Access: Read/write any time

321

MDIS

IBIE

MS/SL

Tx/Rx

NOACK

DMAEN

IBDOZE

RSTA

Reset

100

000

Figure 29-8. I2C Bus Control Register (IBCR)

Table 29-8. IBCR Field Descriptions

Field

Description

MDIS

Module disable. This bit controls the software reset of the entire I2C Bus module.

1 The module is reset and disabled. This is the power-on reset situation. When high, the interface is held in reset,

but registers can still be accessed

0The I2C Bus module is enabled. This bit must be cleared before any other IBCR bits have any effect

Note: If the I2C Bus mdule is enabled in the middle of a byte transfer, the interface behaves as follows: slave mode

ignores the current transfer on the bus and starts operating whenever a subsequent start condition is detected.

Master mode will not be aware that the bus is busy, hence if a start cycle is initiated then the current bus cycle

may become corrupt. This would ultimately result in either the current bus master or the I2C Bus module losing

arbitration, after which, bus operation would return to normal.

IBIE

I-Bus Interrupt Enable.

1 Interrupts from the I2C Bus module are enabled. An I2C Bus interrupt occurs provided the IBIF bit in the status

0 Interrupts from the I2C Bus module are disabled. Note that this does not clear any currently pending interrupt

condition

MS/SL

Master/Slave mode select. Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START signal is

generated on the bus and the master mode is selected. When this bit is changed from 1 to 0, a STOP signal is

generated and the operation mode changes from master to slave. A STOP signal should be generated only if the

IBIF flag is set. MS/SL is cleared without generating a STOP signal when the master loses arbitration.

1 Master Mode

0Slave Mode

Tx/Rx

Transmit/Receive mode select. This bit selects the direction of master and slave transfers. When addressed as a

slave this bit should be set by software according to the SRW bit in the status register. In master mode this bit should

be set according to the type of transfer required. Therefore, for address cycles, this bit will always be high.

1 Transmit

0 Receive

NOACK

Data Acknowledge disable. This bit specifies the value driven onto SDA during data acknowledge cycles for both

master and slave receivers. The I2C module will always acknowledge address matches, provided it is enabled,

regardless of the value of NOACK. Note that values written to this bit are only used when the I2C Bus is a receiver,

not a transmitter.

1 No acknowledge signal response is sent (i.e., acknowledge bit = 1)

0 An acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte of data

RSTA

Repeat Start. Writing a 1 to this bit will generate a repeated START condition on the bus, provided it is the current

bus master. This bit will always be read as a low. Attempting a repeated start at the wrong time, if the bus is owned

by another master, will result in loss of arbitration.

1 Generate repeat start cycle

0 No effect

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