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MAC7200 Datasheet(PDF) 638 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 638 Page - Freescale Semiconductor, Inc |
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638 / 976 page ![]() Functional Description MAC7200 Microcontroller Family Reference Manual, Rev. 2 560 Freescale Semiconductor Reading the IBDR will return the last byte received while the I2C is configured in either master receive or slave receive modes. The IBDR does not reflect every byte that is transmitted on the I2C bus, nor can software verify that a byte has been written to the IBDR correctly by reading it back. In master transmit mode, the first byte of data written to IBDR following assertion of MS/SL is used for the address transfer and should comprise the calling address (in position D7–D1) concatenated with the required R/W bit (in position D0). 29.5.2.6 I2C Interrupt Config Register 29.6 Functional Description 29.6.1 General This section provides a complete functional description of the Inter-Integrated Circuit (I2C). 29.6.2 I-Bus Protocol The I2C Bus system uses a Serial Data line (SDA) and a Serial Clock Line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. A logical AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent. Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer and STOP signal. They are described briefly in the following sections and illustrated in Figure 29-12. Offset 0x0005 Access: Read/write any time 76 54 321 0 R BIIE 0 00 00 0 0 W Reset 000 00 000 Figure 29-11. I2C Bus Interrupt Config Register (IBIC) Table 29-10. IBIC Field Descriptions Field Description 7 BIIE Bus Idle Interrupt Enable bit. This config bit can be used to enable the generation of an interrupt once the I2C bus becomes idle. Once this bit is set, an IBB high-low transition will set the IBIF bit. This feature can be used to signal to the CPU the completion of a STOP on the I2C bus. 1 Bus Idle Interrupts enabled 0 Bus Idle Interrupts disabled 6–0 Reserved for future use. A read will return 0; should be written as 0. |
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