MAC7200 datasheet(636/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

558

Freescale Semiconductor

29.5.2.4

I2C Status Register

DMAEN

DMA Enable. When this bit is set, the DMA TX and RX lines will be asserted when the I2C module requires data to

be read or written to the data register. No Transfer Done interrupts will be generated when this bit is set, however

an interrupt will be generated if the loss of arbitration or addressed as slave conditions occur. The DMA mode is only

valid when the I2C module is configured as a Master and the DMA transfer still requires CPU intervention at the start

and the end of each frame of data. See the DMA Application Information section for more details.

1 Enable the DMA TX/RX request signals

0 Disable the DMA TX/RX request signals

IBSDOZE

I-Bus Interface Stop in DOZE mode.

1Halt I2C Bus module clock generation (if DOZE mode signal asserted)

0I2C Bus module clock operates normally

Note: If the IBSDOZE mode is SET, the I2C module will enter DOZE mode when the DOZE signal is asserted, if

there are no current transactions on the bus. The I2C module would then signal to the system that the clock can

be shut down.

If it were the case that the IBDOZE bit was cleared when the DOZE signal was asserted, the I2C Bus module clock

would remain alive, and any current transactions would continue as normal.

Offset 0x0003

Access: Read-only any time1

1. With the exception of IBIF and IBAL, which are software clearable.

321

TCF

IAAS

IBB

IBAL

SRW

IBIF

RXAK

Reset

100

000

Figure 29-9. I2C Bus Status Register(IBSR)

Table 29-9. IBSR Field Descriptions

Field

Description

TCF

Transfer complete. While one byte of data is being transferred, this bit is cleared. It is set by the falling edge of the

9th clock of a byte transfer. Note that this bit is only valid during or immediately following a transfer to the I2C module

or from the I2C module.

1 Transfer complete

0 Transfer in progress

IAAS

Addressed as a slave. When its own specific address (I-Bus Address Register) is matched with the calling address,

this bit is set. The CPU is interrupted provided the IBIE is set. Then the CPU needs to check the SRW bit and set its

Tx/Rx mode accordingly. Writing to the I-Bus Control Register clears this bit.

1 Addressed as a slave

0 Not addressed

IBB

Bus busy. This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a STOP signal

is detected, IBB is cleared and the bus enters idle state.

1Bus is busy

0 Bus is Idle

Table 29-8. IBCR Field Descriptions (Continued)

Field

Description

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