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MAC7200 Datasheet(PDF) 876 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 876 Page - Freescale Semiconductor, Inc |
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876 / 976 page ![]() Introduction MAC7200 Microcontroller Family Reference Manual, Rev. 2 798 Freescale Semiconductor 34.1.2 Features The Port Integration Module includes these distinctive features: • Select between GPIO, interrupt or peripheral functionality on a pin-by-pin basis • Register interface for both port wide and pin data reads and writes • 6 independent 16-bit ports (Port A, B, C, D, F, G), with each pin having the following features: — Peripheral or GPIO Mode selection, with up to 3 peripherals per pin — Input/Output selection — 5V output drive with three selectable slew rates (Disabled, Slow, Fast) — 5V digital inputs — Selectable pull-up or pull-down — Selectable open drain for wired-or connections — Selectable interrupt capability (with glitch filtering and interrupt mask) • Control of ATD digital inputs (Port E) — Selectable interrupt capability (with glitch filtering and interrupt mask) • Control of the TCK, TMS, TDI and TDO pads — Input/Output selection — 5V output drive with three selectable slew rates (Disabled, Slow, Fast) (TDO only) — 5V digital inputs — Selectable pull-up or pull-down (TCK, TMS and TDI only) 34.1.3 Modes of Operation 34.1.3.1 Peripheral Mode (CONFIG::MODE[1:0] ≠ 0 0) In this mode, the peripheral drives all data and control signals to the pad, with the exception of the Slew Rate (SRE1/SRE0) signals, which are always driven by the SLEWDIS and SLEW bits in the corresponding CONFIGxx register in the PIM. Table 34-3. PIM Peripheral Mode Configuration Register / Field Definition PORTDATA/PINDATAxx This value has no effect. PORTIR This read-only register returns the value currently driven on the pin by the peripheral (output) or by an external device (input). DDR This register bit has no effect. SLEWDIS/SLEW Slew Rate control bits: Controls the slew rate of the pin (output only). SLEWDIS = 0 Slew Rate control is disabled SLEW 0 = Fast slew rate, 1 = Slow slew rate PULL These two register bits have no effect. |
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