MAC7200 datasheet(969/976 Pages) FREESCALE

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Flash Characteristics

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

891

Figure A-15 shows timing for the values in Table A-34 and Table A-35.

Figure A-15. I2C Input/Output Timings

A.18

Flash Characteristics

NOTE

Unless otherwise noted the abbreviation NVM (Non-Volatile Memory) is

used for both the Flash Main Array and the Shadow Block.

Table A-35. I2C Output Timing Specifications between SCL and SDA

Num

Rating

Min

Typ

Max

Units

AA11

1. Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum

frequency (IFDR = $20) results in minimum output timings as shown in Table A-35. The I2C interface is

designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual

position is affected by the prescale and division values programmed into the IFDR; however, the numbers

given in Table A-35 are minimum values.

D Start condition hold time

—

tPERIPH

2. tPERIPH = 1/fPERIPH. See parameter C8.

AA2 1

D Clock low period

—

tPERIPH

AA3 3

3. Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the

time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up resistor

values.

D SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V)

—

nµs

AA4 1

D Data hold time

—

tPERIPH

AA5 4

4. Specified at a nominal 50-pF load.

D SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V)

—

AA6 1

D Clock high time

—

tPERIPH

AA7 1

D Data setup time

—

tPERIPH

AA8 1

D Start condition setup time (for repeated start

condition only)

—

tPERIPH

AA9 1

D Stop condition setup time

—

tPERIPH

SCL

AA2

AA6

AA1

AA4

AA5

AA7

AA8

AA3

AA9

SDA

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