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6402 Datasheet(PDF) 235 Page - Intel Corporation |
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6402 Datasheet(HTML) 235 Page - Intel Corporation |
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235 / 250 page ![]() Intel® 6400/6402 Advanced Memory Buffer Datasheet 235 Registers 14.8.2.9 SBFIBPATTBUF2: SB Intel IBIST Pattern Buffer 2 Register This optional register contains the pattern bits used in Intel IBIST operations. Only the least significant 24 bits are used. This user specified pattern goes out on to the link with the least-significant 12 bits as the first frame and the most significant 12 bits as the second frame. 14.8.2.10 SBFIBPATT2EN: SB Intel IBIST Pattern Buffer 2 Enable This optional register specifies which lanes will carry the pattern specified in SBFIBPATTBUFF2. 14.8.2.11 SBFIBINIT: SB Intel IBIST Initialization Register This register control southbound Intel IBIST Testing. Device: NodeID Function: 6 Offset: A0h Bit Attr Default Description 31:24 RV 00h Reserved 23:0 RWST fd3302h IBPATBUF2: IBIST Pattern Buffer 2 Pattern buffer storing the default and the user programmable pattern. Default: fd3302h Device: NodeID Function: 6 Offset: A4h Bit Attr Default Description 31:10 RV 00h Reserved 9:0 RWST 000h SBFIBPATT2EN: IBIST Pattern Buffer 2 enable Per lane enable for driving pattern buffer 2. Device: NodeID Function: 6 Offset: B0h Bit Attr Default Description 31 RV 0 Reserved 30:21 RWST 0c8h SBTS0CNT: Southbound TS0 Count Number of TS0 sequences to transmit. 20:13 RWST 01h SBTS1CNT: Southbound TS1 Count Number of TS1 sequences to transmit. If TS1CNT[7] = 1; (TS1CNT >= 128) Intel IBIST will loop forever If TS1CNT[7] = 0; (TS1CNT <128) Intel IBIST will loop TS1CNT times 12:3 RWST 100h SBDISCNT: Southbound Disable State Count Number of cycles to remain in disable state. 2RWST1 SBCALIBEN: Southbound Calibration Enable 1 - Perform FBD Calibration. 1RV0 Reserved 0RWST0 SBIBISTINITEN: IBIST Initialization Enable 1 - Start IBIST Testing with Southbound Transmitter as the host. |
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