6402 datasheet(237/250 Pages) INTEL

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

237

Registers

14.8.3.2

NBFIBPGCTL: NB Intel IBIST Pattern Generator Control Register

This register contains bits to control the operation of the Intel IBIST pattern generator.

All counts are in 24 bit increments.

2RWCST

COMPLETE: IBIST done flag

0: Not done

1: Done

1RWST

MSTRMD: Master Mode Enable

When this bit is set along with IBISTR, the Intel IBIST transmit engine is

enabled to transmit Intel IBIST patterns.

0: Disable Master mode.

1: Enable master mode.

0RWST

IBISTR: IBIST Start

When set, Intel IBIST starts transmitting after the TS1 header is recognized

during the next link initialization sequence. and MSTRMD bit is set.This bit also

enables the receive engine to start looking for the start delimiter during TS1

training set. This bit is reset when Intel IBIST receiver is done. The Intel IBIST

transmit and receive engines can be stopped by setting this bit to 0.

0: Stop IBIST transmitter

1: Start IBIST transmitter

Device:

NodeID

Function: 6

Offset:

C0h

Bit

Attr

Default

Description

Device:

NodeID

Function: 6

Offset:

C4h

Bit

Attr

Default

Description

31:26

RWST

0Fh

OVRLOOPCNT: Overall Loop Count

0h: Reserved

1h-3Fh: Number of times to loop all the patterns.

25:21

RWST

00h

CNSTGENCNT: Constant Generator Loop Counter

00h: Disable constant generator output

01h: 1Fh The number of times the constant generator counter pattern should loop

before going to the next component. Each count represents 24 bits of 1’s or 0’s.

RWST

CNSTGENSET: Constant Generator Setting

0: Generate 0

1: Generate 1

19:13

RWST

0Fh

MODLOOPCNT: Modulo-N Loop Counter

Each count represents 24 bits of the pattern specified by MODPERIOD.

00h: Disable Pattern Output

01h: 7Fh The number of times the Pattern Buffer should loop before going to the

next component.

12:10

RWST

001b

MODPERIOD: Period of the Modulo-N counter

Each encoding transmits a 24-bit pattern as specified below. All other encodings are

reserved.

001: L/2 - 0101_0101_0101_0101_0101_0101

010: L/4 - 0011_0011_0011_0011_0011_0011

011: L/6 - 0001_1100_0111_0001_1100_0111

100: L/8 - 0000_1111_0000_1111_0000_1111

110: L/24 - 0000_0000_0000_1111_1111_1111

9:3

RWST

0Fh

PATTLOOPCNT: Pattern Buffer Loop Counter

00h: Disable Pattern Output

01h: 7Fh The number of times the Pattern Buffer (IBPATTBUF) should be repeated

before going to the next component.

6402 Datasheet(PDF) 237 Page - Intel Corporation

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