FS6131 datasheet(12/44 Pages) ONSEMI

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FS6131

0.0

5.0

10.0

15.0

20.0

25.0

204060

CLKP/CLKN PECL Output Current (mA)

Figure 12: IPRG to CLKP/CLKN Current

5.0 I

2C-bus Control Interface

This device is a read/write slave device meeting all Philips I2C-bus specifications except a "general call." The bus has to be

controlled by a master device that generates the serial clock SCL, controls bus access and generates the START and

STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but the

master device determines which mode is activated. A device that sends data onto the bus is defined as the transmitter, and

a device receiving data as the receiver. I2C-bus logic levels noted herein are based on a percentage of the power supply (VDD). A logic-

one corresponds to a nominal voltage of VDD, while a logic-zero corresponds to ground (VSS).

5.1 Bus Conditions

Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable

whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START

or STOP condition. The following bus conditions are defined by the I2C-bus protocol.

5.1.1. Not Busy

Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy.

5.1.2. START Data Transfer

A high to low transition of the SDA line while the SCL in-put is high indicates a START condition. All commands to the device must be

preceded by a START condition.

5.1.3. STOP Data Transfer

A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be

followed by a STOP condition.

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FS6131 Datasheet(PDF) 12 Page - ON Semiconductor