FS6131 datasheet(35/44 Pages) ONSEMI

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FS6131

However, the full signal amplitude may take up to twice as long as the propagation delay of the line to develop, reducing noise immunity

during the half-amplitude period. Note that the voltage at the receive end must add up to a signal amplitude that meets the receiver

switching thresholds. The slew rate of the signal may be reduced due to the additional RC delay of the load capacitance and the line

impedance. Also, note that the output driver impedance will vary slightly with the output logic state (high or low).

11.3 Serial Communications

Connection of devices to a standard-mode implementation of the I2C-bus is similar to that shown in Figure 23. Selection of the pull-up

resistors (RP) and the optional series resistors (RS) on the SDA and SCL lines depends on the supply voltage, the bus capacitance and

the number of connected devices with their associated input currents.

Control of the clock and data lines is done through open drain/collector current-sink outputs, and thus requires external pull-up resistors

on both lines.

A guideline is

bus

where tr is the maximum rise time (minus some margin) and Cbus is the total bus capacitance. Assuming an I2C controller and eight to ten

other devices on the bus, including this one, results in values in the 5kW to 7kW range. Use of a series resistor to provide protection

against high voltage spikes on the bus will alter the values for RP.

SDA

SCL

Data In

Data Out

Clock Out

TRANSMITTER

Data In

Data Out

RECEIVER

Clock In

(optional)

Figure 23: Connections to the Serial Bus

11.3.1. For More Information

More information on the I

2C -bus can be found in the document The I2C-bus And How To Use It (Including Specifications), available

from Philips Semiconductors at http://www-us2.semiconductors.philips.com.

Rev. 4 | Page 35 of 44 | www.onsemi.com

FS6131 Datasheet(PDF) 35 Page - ON Semiconductor