FS6131 datasheet(41/44 Pages) ONSEMI

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FS6131

The output clock frequency is calculated as

MHz

800

kHz

CLK

For best performance, program the post divider (NPx) modulus to allow the VCO to operate at a nominal frequency that is at least

70MHz but less than 230MHz. The VCO frequency (fVCO) can be calculated by

CLK

VCO

Selecting the post divider modulus of NPx=6 is a reasonable solution, although there are a number of values that will work. Try to keep

5000

to avoid divider values from becoming too large. The settings place the VCO frequency at about 72MHz.

Calculate the ideal charge pump current (Ipump) as

VCO

HSYNC

pump

kHz

where Rlf is the external loop filter series resistor, Clf is the external loop filter series capacitor and AVCO is the VCO gain. The VCO gain is

either

AVCO=125MHz/V if the high range is selected, or

AVCO=75MHz/V if the low range is selected.

See Table 15 for more information on the VCO range. With fhsync=15kHz, Clf=0.015mF, Rlf=15kW, NF=800, NPx=6, and AVCO=125MHz/V,

the charge pump current is 24mA. A 220pF cap across the entire loop filter is also helpful.

14.2 Example Programming

To generate 800 pixel clocks between HSYNC pulses occurring on the line reference signal every 15kHz, program the following (refer

to Figure 26):

• Clear the OSCTYPE bit to 0

• Turn off the crystal oscillator via XLROM=7

• Set the PFD inputs to select the REF and FBK pins via PDREF=1 and PDFBK=1

• Set NP1=2, NP2=3 and NP3=1 for a combined post divider modulus of NPx=6 via POST1[1:0], POST2[1:0] and POST3[1:0].

• Select the external loop filter via EXTLF=1

• Set XLVTEN=0 and XLPDEN=1 to disable the VCXO fine tune and the crystal loop phase frequency detector

• Set VCOSPD=1 to select the VCO low speed range

• Set MLCP[1:0] to 3 to select the 32mA range

The output clock frequency fCLK is 12MHz, with an internal VCO frequency of 72MHz. Note that the crystal loop was unused in this

application.

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FS6131 Datasheet(PDF) 41 Page - ON Semiconductor