FS6131 datasheet(36/44 Pages) ONSEMI

36 / 44 page

Rev. 4 | Page 36 of 44 | www.onsemi.com

FS6131

12.0 Device Application: Stand-Alone Clock Generation

The length of the reference and feedback dividers, their granularity and the flexibility of the post divider make the FS6131 the most

flexible monolithic stand-alone PLL clock generation device available. The effective block diagram of the FS6131 when programmed for

stand-alone mode is shown in Figure 24.

The source of the feedback divider in the stand-alone mode is the output of the VCO. By dividing the input reference frequency down by

reference divider (NR), then multiplying it up in the main loop through the feedback divider (NF), and finally dividing the main loop output

frequency by the post divider (NPx), we have the defining relationship for this mode. The equation for the output clock frequency (fCLK)

can be written as

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

REF

CLK

where the reference source frequency (fREF) can be either supplied by the VCXO or applied to the REF pin.

Great flexibility is permitted in the programming of the FS6131 to achieve exact desired output frequencies since three integers are

involved in the computation.

12.1 Example Calculation

A Visual BASIC program is available to completely program the FS6131 based on the given parameters.

Suppose that the reference source frequency is 14.318MHz and the desired output frequency is 100MHz.

First, factor the 14.318MHz reference frequency (which is four times the NTSC television color sub-carrier) into prime numbers. The

exact expression is

14318181

REF

FS6131

VCXO

Divider

(optional)

CRYSTAL LOOP

MAIN LOOP

VCXO

XOUT

XIN

Control

ROM

XTUNE

Reference

Divider

Phase-

Frequency

Detector

Charge

Pump

DOWN

REF

FBK

Phase-

Frequency

Detector

Charge

Pump

DOWN

Internal

Loop

Filter

EXTLF

I2C

Interface

SCL

SDA

ADDR

Registers

POST3[1:0]

POST2[1:0]

POST1[1:0]

REFDIV[11:0]

EXTLF

PDREF

PDFBK

VCOSPD,

OSCTYPE

LFTC

MLCP[1:0]

XLCP[1:0]

XLROM[2:0]

XLPDEN,

XLSWAP

REFDSRC

XCT[3:0],

XLVTEN

REF)

VCO)

LOCK/

IPRG

Post

Divider

Px)

Voltage

Controlled

Oscillator

Lock

Detect

CMOS

(optional)

STAT[1:0]

OM[1:0]

Clock

Gobbler

GBL

(optional)

Feedback

Divider (N

FBKDIV[14:0]

FBKDSRC[1:0]

CMOS/PECL

Output

CLKN

CLK)

CLKP

IPRG

Figure 24: Block Diagram: Stand-Alone Clock Generation

FS6131 Datasheet(PDF) 36 Page - ON Semiconductor

FS6131 Datasheet(HTML) 36 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL