FS6131 datasheet(38/44 Pages) ONSEMI

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FS6131

13.0 Device Application: Line-Locked Clock Generation

Line-locked clock generation, as used here, refers to the process of synthesizing a clock frequency that is some integer multiple of the

horizontal line frequency in a graphics system. The FS6131 is easily configured to perform that function, as shown in Figure 25.

A line reference signal (fHSYNC) is applied to the REF input for direct application to the main loop PFD. The feedback divider (NF) is

programmed for the desired number of output clocks per line.

The source for the feedback divider is selected to be the output of the post divider (NPx) so that the edges of the output clock maintain a

consistent phase alignment with the line reference signal. The modulus of the post divider should be selected to maintain a VCO

frequency that is comfortably within the operating range noted in Table 15.

13.1 Example Calculation

A Visual BASIC program is available to completely program the FS6131 based on the given parameters.

Suppose that we wish to reconstruct the pixel clock from a VGA source. This is a typical requirement of an LCD projection panel

application.

First, establish the total number of pixel clocks desired between horizontal sync (HSYNC) pulses. The number of pixel clocks is known

as the horizontal total, and the feedback divider is programmed to that value. In this example, choose the horizontal total to be 800.

Next, establish the frequency of the HSYNC pulses (fHSYNC) on the line reference signal for the video mode. In this case, let

fHSYNC=31.5kHz. The output clock frequency fCLK is calculated to be:

MHz

175

800

kHz

HSYNC

CLK

Reference

HSYNC

FS6131

VCXO

Divider

(optional)

CRYSTAL LOOP

MAIN LOOP

VCXO

XOUT

XIN

Control

ROM

XTUNE

Reference

Divider

Phase-

Frequency

Detector

Charge

Pump

DOWN

REF

FBK

Phase-

Frequency

Detector

Charge

Pump

DOWN

Feedback

Divider (N

Internal

Loop

Filter

EXTLF

I2C

Interface

SCL

SDA

ADDR

Registers

POST3[1:0],

POST2[1:0],

POST1[1:0]

REFDIV[11:0]

FBKDIV[14:0]

EXTLF

PDREF

PDFBK

VCOSPD,

OSCTYPE

LFTC

MLCP[1:0]

XLCP[1:0]

XLROM[2:0]

XLPDEN,

XLSWAP

REFDSRC

XCT[3:0],

XLVTEN

REF)

VCO)

LOCK/

IPRG

Post

Divider

Px)

Voltage

Controlled

Oscillator

Lock

Detect

CMOS

(optional)

STAT[1:0]

OM[1:0]

Clock

Gobbler

GBL

(optional)

FBKDSRC[1:0]

CMOS/PECL

Output

CLKN

CLK)

CLKP

IPRG

Figure 25: Block Diagram: Line-Locked Clock Generation

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