FS6131 datasheet(40/44 Pages) ONSEMI

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Rev. 4 | Page 40 of 44 | www.onsemi.com

FS6131

14.0 Device Application: Genlocking

Genlocking refers to the process of synchronizing the horizontal sync pulses (HSYNC) of a target graphics system to the HSYNC of a

source graphics system. In a genlocked mode, the FS6131 increases (or decreases) the frequency of the VCO until the FBK input is

frequency matched and phase-aligned to the frequency applied to the REF input. Since the feedback divider is within the graphics

system and the graphics system is the source of the signal applied to the FBK input of the FS6131, the graphics system is effectively

synchronized to the REF input as shown in Figure 26.

To configure the FS6131 for genlocking, the REF input (pin 12) and the FBK input (pin 13) are switched directly onto the feedback input

of the PFD. The reference and feedback dividers are not used.

The output clock frequency is:

total

horizontal

HSYNC

CLK

The only remaining task is to select a post divider modulus (NPx) that allows the VCO frequency to be within its nominal range.

14.1 Example Calculation

A Visual BASIC program is available to completely program the FS6131 based on the given parameters.

The FS6131 is being used to genlock an LCD projection panel system to a VGA card-generated HSYNC. The total number of pixel

clocks generated by the VGA card, known as the horizontal total, are 800. Therefore, the LCD panel graphics system that is clocked by

the FS6131 is set to divide the output clock frequency (fCLK) by 800. The input HSYNC reference frequency (fHSYNC) is 15kHz.

Video Graphics System

System HSYNC

Clock In

Reference

HSYNC

FS6131

VCXO

Divider

(optional)

CRYSTAL LOOP

MAIN LOOP

VCXO

XOUT

XIN

Control

ROM

XTUNE

Reference

Divider

Phase-

Frequency

Detector

Charge

Pump

DOWN

REF

FBK

Phase-

Frequency

Detector

Charge

Pump

DOWN

Feedback

Divider (N

Internal

Loop

Filter

EXTLF

I2C

Interface

SCL

SDA

ADDR

Registers

POST3[1:0],

POST2[1:0],

POST1[1:0]

REFDIV[11:0]

FBKDIV[14:0]

FBKDSRC[1:0]

EXTLF

PDREF

PDFBK

VCOSPD,

OSCTYPE

LFTC

MLCP[1:0]

XLCP[1:0]

XLROM[2:0]

XLPDEN,

XLSWAP

REFDSRC

XCT[3:0],

XLVTEN

CLK)

VCO)

IPRG

LOCK/

IPRG

Post

Divider

Px)

Voltage

Controlled

Oscillator

Lock

Detect

CMOS

(optional)

STAT[1:0]

OM[1:0]

Clock

Gobbler

GBL

(optional)

CMOS/PECL

Output

CLKN

CLK)

CLKP

Figure 26: Block Diagram: Genlocking

FS6131 Datasheet(PDF) 40 Page - ON Semiconductor

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