FS6131

15.0 Device Application: Telecom Clock Regenerator

The FS6131 can be used as a clock regenerator as shown in Figure 28. This mode uses the VCXO in its own phase-locked loop,

referred to as the crystal loop. The VCXO provides a "de-jittered" multiple of the reference frequency at the REF pin (usually 8kHz in

telecom applications) for use by the main loop. In essence, the crystal loop "cleans up" the reference signal for the main loop.

The control ROM for the VCXO divider is preloaded with the most common ratios to permit locking of most standard

telecommunications crystals to an 8kHz signal applied to the REF pin. The de-jittered multiple of the reference frequency from the

VCXO is then supplied to the reference divider in the main loop. The reference divider, along with the feedback divider, can be

programmed to achieve the desired output clock frequency.

15.1 Example Calculation

A Visual BASIC program is available to completely program the FS6131 based on the given parameters.

In this example, an 8kHz reference frequency is supplied to the FS6131 and an output clock frequency of 51.84MHz is desired.

First, select the frequency at which the VCXO will operate from Table 10. The table shows the external crystal frequency options

available to choose from, since the VCXO runs at the crystal frequency. While the main loop can be programmed to work with any of

the frequencies in the table, the best performance will be achieved with the highest frequency at the main loop PFD.

R

VCXO

MLpfd

N

f

f

=

8kHz IN

(typical)

FS6131

VCXO

Divider

(optional)

(optional)

CRYSTAL LOOP

MAIN LOOP

VCXO

XOUT

XIN

Control

ROM

XTUNE

Reference

Divider

(N

Phase-

Frequency

Detector

Charge

Pump

UP

DOWN

REF

FBK

Phase-

Frequency

Detector

Charge

Pump

UP

DOWN

Feedback

Internal

Loop

Filter

EXTLF

Interface

SCL

SDA

ADDR

Registers

POST3[1:0],

POST2[1:0],

POST1[1:0]

REFDIV[11:0]

FBKDIV[14:0]

EXTLF

PDREF

PDFBK

VCOSPD,

OSCTYPE

LFTC

MLCP[1:0]

XLCP[1:0]

XLROM[2:0]

XLPDEN,

XLSWAP

REFDSRC

XCT[3:0],

XLVTEN

(f

(f

LOCK/

IPRG

Post

Divider

(N

Voltage

Controlled

Oscillator

Lock

Detect

CMOS

(optional)

STAT[1:0]

OM[1:0]

Clock

Gobbler

GBL

(optional)

CMOS/PECL

Output

CLKN

(f

CLKP

FBKDSRC[1:0]

R

LF

C

LF

R

IPRG

C

LP

Figure 27: Block Diagram: Telecom Clock Generator

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