FS6131

FS6131

VCXO

Divider

(optional)

(optional)

CRYSTAL LOOP

MAIN LOOP

VCXO

XOUT

XIN

Control

ROM

XTUNE

Reference

Divider

(N

Phase-

Frequency

Detector

Charge

Pump

UP

DOWN

REF

FBK

Phase-

Frequency

Detector

Charge

Pump

UP

DOWN

Feedback

Internal

Loop

Filter

EXTLF

Interface

SCL

SDA

ADDR

Registers

POST3[1:0]

POST2[1:0]

POST1[1:0]

REFDIV[11:0]

FBKDIV[13:0]

EXTLF

PDREF

PDFBK

VCOSPD,

OSCTYPE

LFTC

MLCP[1:0]

XLCP[1:0]

XLROM[2:0]

XLPDEN,

XLSWAP

REFDSRC

XCT[3:0],

XLVTEN

(f

(f

LOCK/

IPRG

Post

Divider

(N

Voltage

Controlled

Oscillator

Lock

Detect

CMOS

(optional)

STAT[1:0]

OUTMUX[1:0]

Clock

Gobbler

GBL

(optional)

FBKDSRC[1:0]

CMOS/PECL

Output

CLKN

(f

CLKP

R

LF

C

LF

C

LP

11

00

10

01

01

00

10

11

1

0

1

0

0

1

1

0

1

0

Figure 2: Block Diagram

Table 1: Pin Descriptions

Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI

DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin

Pin

Type

Name

Description

1

DI

SCL

Serial interface clock (requires an external pull-up)

2

DIO

SDA

Serial interface data input/output (requires an external pull-up)

3

DI

ADDR

Address select bit (see Section 5.2.1)

4

P

VSS

Ground

5

AI

XIN

VCXO feedback

6

AO

XOUT

VCXO drive

7

AI

XTUNE

VCXO tune

8

P

VDD

Power supply (+5V)

9

DIO

LOCK/IPRG

Lock indicator / PECL current drive programming

10

AI

EXTLF

External loop filter

11

P

VSS

Ground

12

DI

REF

Reference frequency input

13

DI

FBK

Feedback input

14

P

VDD

Power supply (+5V)

15

DO

CLKP

Differential clock output (+)

16

DO

CLKN

Differential clock output (-)

Rev. 4 | Page 2 of 44 | www.onsemi.com