LC07424LP datasheet(24/32 Pages) SANYO

24 / 32 page

LC07424LP

Audio data format, Other

ADF_BCLK

: Audio Data Format BCLK

ADF_MODE

: Audio Data Format MODE

ADF_DAC_INV : Audio Data Format DAC data INVert

ADF_ADC_INV : Audio Data Format ADC data INVert

DE_EN: De-Emphasis filter ENable

ADF_FS

: Audio Data Format Frequency Sampling

ADF_LB

: Audio Data Format Loop Back

ADF_MASTER : Audio Data Format MASTER mode

ADRS

Bit

Name

INIT

Description

09h

[4]

ADF_BCLK

Bit clock frequency setting of audio data format

See Table 8.3.

[1:0]

ADF_MODE[1:0]

00b

Audio data format setting

See Table 8.3.

No.A1619-24/32

[7]

ADF_DAC_INV

DAC input data inverted setting

1: Inverted 0: Non-inversion

0Ah

[6]

ADF_DAC_INV

ADC output data inverted setting

1: Inverted 0: Non-inversion

[4]

DE_EN

De-Emphasis Filter setting

1: De-Emphasis Filter Effective

0: De-Emphasis Filter Not effective

[3:2]

ADF_FS[1:0]

00b

Sampling Frequency Setting

11: Set prohibition

10: 44.1kHz

01: 32kHz

00: 48kHz

[1]

ADF_LB

Loop back mode select. See Fig. 8.1.

1: ON (ADC output data becomes the DAC input data.)

0: OFF (Normal operation. DAC_DIN pin input becomes the

DAC input data.)

[0]

ADF_MASTER

Master / Slave mode setting (IO control of BCLK and LRCLK pins )

1: Master mode (BCLK and LRCLK pins for output)

0: Slave mode (BCLK and LRCLK pins for input)

"7. Audio data format."

Loop back function

Table 8.3 ADF setting

This function connects internally ADC_DOUT and DAC_DIN signals.

[ADF_MODE]

[ADF_BCLK]

This will enable the ADC input signal to go through to the DAC output.

Set prohibition

In this case, the ADC_DOUT pin output signal is effective,

Backward

justification 32fs

but the DAC_DIN pin input becomes ineffective.

Forward

justification 32fs

[ADF_LB]

Selector, Mixer circuit

SEL_L

: SELctor Lch

SEL_R

: SELctor Rch

MIX_MONO

: MIXer MONO

ADRS

Bit

Name

Init

Description

0Bh

[7:6]

SEL_L

10b

Selector circuit. Lch signal selection

10: DAC output selection 01: ALC / PGA output selection 11, 00: Set prohibition

[5:4]

SEL_R

10b

Selector circuit. Rch signal selection

10: DAC output selection 01: ALC / PGA output selection 11, 00: Set prohibition

[1:0]

MIX_MONO

11b

MIX circuit, Setting

11: Lch+Rch setting 10: Rch setting 01: Lch setting 00: Set prohibition

I2S 32fs

ADC

I2S IF

ADC_DOUT pin

Backward

justification 64fs

Forward

justification 64fs

I2S 64fs

DAC_DIN pin

OFF

DAC

Fig.8.1. Loop back circuit

LC07424LP Datasheet(PDF) 24 Page - Sanyo Semicon Device

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