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LC07424LP Datasheet(PDF) 28 Page - Sanyo Semicon Device

Part # LC07424LP
Description  CMOS IC Audio CODEC with Video Driver
PDF  32 Pages
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Manufacturer  SANYO [Sanyo Semicon Device]
Direct Link  https://www.sanyo-av.com/us/
Logo SANYO - Sanyo Semicon Device

LC07424LP Datasheet(HTML) 28 Page - Sanyo Semicon Device

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LC07424LP
Control to reduce the POP sound
‹Note› [xxxx] is a register name.
The POP sound can be reduced by performing start/stop in the timing shown below.
Reference power supply, line out start / stop sequence
[VREF_BIAS[1]]
[VREF_BIAS[0]]
[LO_PDX]
[LO_MUTE]
t2
t3
t3
t2
t4b
t1
t4a
(0.5)VDDh
(0.5)VDDana
(0.5)VDDh
Common reference power supply
No.A1619-28/32
Vref_H_C pin
Vref_C pin
Line_out input signal
LOUT_L pin
LOUT_R pin
Line_out circuit
•
Recommendation value
t1 › 300ms (Rapid charge period with the Vref_H_C pin connection capacity of 1μF and the Vref_C pin
connection capacity of 4.7μF)
t2 › 0ms
t3 › 1ms
(Waiting time of MUTE ON / OFF)
t4a › 300ms
(Pull down period)
t4b › 1ms
(Pull down period, at already when LOUT_L, LOUT_R pin is GND level.)
•
It makes it to 0Fh: [LO_VREFSW] = 1, usually.
•
[LO_VREFSW] function at power down (LO_PDX = 0)
[LO_VREFSW] = 1: LOUT_L, LOUT_R pin becomes VREF level output
Speaker Amplifier Start / Stop Sequence
[LO_VREFSW] = 0: LOUT_L, LOUT_R pin becomes Hi-Z
•
Recommendation value
t2
t3
t1
t4
(0.5)VDDh
t2
t2
t2
[SP_PDX]
[SP_OUTEN]
Speaker amplifier
input signal
SPP,SPN pin
(Speaker output)
t1 › 1ms (Speaker bias start-up time)
t2: [SP_SSC] set time (200ms / 100ms / 50ms / 10ms)
t3 › 1ms
t4 › 1ms
•
[SP_OUT_EN] must be set to 0 when power down ([SP_PDX] = 0) mode.



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