TLE5012 datasheet(26/64 Pages) INFINEON

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TLE5012

Specifications

Final Data Sheet

V 1.0, 2010-11

3.4.6

Clock Supply (CLK Timing Definition)

If the external clock supply is selected, the clock signal input CLK must fulfill certain requirements:

•

The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse

width and must be spike filtered.

•

The duty cycle factor should be 0.5 but can deviate to the values limited by tCLKh(f_min) and tCLKl(f_min).

•

The PLL is triggered at the positive edge of the clock; if more than 2 edges are missing, a chip reset is

generated automatically.

Figure 14

External CLK timing definition

Table 11

CLK timing specification

Parameter

Symbol

Values

Unit

Note / Test Condition

Min.

Typ.

Max.

Input frequency

fCLK

3.8

4.0

4.2

MHz

CLK duty cycle1)2)

1) Minimum Duty Cycle Factor: tCLKh(f_min) / tCLK(f_min) with tCLK(f_min)= 1 / fCLK(f_min)

2) Maximum Duty Cycle Factor: tCLKh(f_max) / tCLK(f_min) with tCLKh(f_max)= tCLK(f_min) - tCLKl(min)

CLKDUTY

CLK rise time

tCLKr

From VL to VH

3) Not subject to production test - verified by design/characterization

CLK fall time

tCLKf

From VH to VL

Digital clock

fDIG

22.8

25.2

MHz

Internal oscillator frequency

fCLK

3.8

4.0

4.2

MHz

tCLKh

tCLKl

tCLK

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