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TLE5012 Datasheet(PDF) 34 Page - Infineon Technologies AG |
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TLE5012 Datasheet(HTML) 34 Page - Infineon Technologies AG |
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34 / 64 page ![]() TLE5012 Specifications Final Data Sheet 34 V 1.0, 2010-11 3.5.1.3.1 TLE5012 Register Status Register STAT Offset Reset Value Status Register 00 H 8001 H Field Bits Type Description RD_ST 15 r Read Status 0B status values not changed since last readout 1B status values changed Reset: 1B S_NR 14:13 w Slave Number is given at startup by the external circuit of IFA and IFB and can be changed via SSC-IF Reset: 00B NO_GMR_A 12 ru No valid GMR Angle Value Cyclic check of DSPU output. 0B valid GMR angle value on the interface 1B no valid GMR angle value on the interface (e.g test vectors) Reset: 0B NO_GMR_XY 11 ru No valid GMR XY Values Cyclic check of ADC input. 0B valid GMR_XY values on the ADC input 1B no valid GMR_XY values on the ADC input (e.g. test vectors) Reset: 0B S_ROM 10 r Status ROM 1) Check of ROM-CRC at startup. After fail DSPU does not start. SPI access possible. 0B CRC OK 1B CRC fail or running Reset: 0B 15 8 7 0 15 15 r RD_ST 14 13 w S_NR 12 12 ru NO_GMR_ A 11 11 ru NO_GMR_ XY 10 10 r S_ROM 99 ru S_ADCT 88 Res 77 ru S_MAGOL 66 ru S_XYOL 55 ru S_OV 44 ru S_DSPU 33 ru S_FUSE 22 ru S_VR 11 ru S_WD 00 ru S_RST |
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