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WM8961 Datasheet(PDF) 46 Page - Wolfson Microelectronics plc |
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WM8961 Datasheet(HTML) 46 Page - Wolfson Microelectronics plc |
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46 / 116 page ![]() WM8961 Pre-Production w PP, August 2009, Rev 3.1 46 HEADPHONE PLAYBACK MODES Headphone playback can be optimised for lowest power or best SNR, depending on the application requirements. STANDARD MODE Headphone playback with the best compromise between performance and power consumption can be enabled using the default DAC to Headphone Playback power on sequence as implemented at control write sequencer address 0, as detailed in “Control Write Sequencer”. LOW POWER MODE Headphone playback optimised for lower power consumption can be enabled. This results in a very slight reduction in headphone driver performance. The register setting listed in Table 32 can be added to the power up sequence in order to implement this mode. Note that this register setting must take place before the charge pump is enabled. See the “Charge Pump” section. If the write sequencer is used to configure the DAC to HP path, this register write must take place before the write sequencer is enabled and triggered. REGISTER ADDRESS BITS LABEL SETTING DESCRIPTION R82 (52h) Charge Pump B 1:0 CP_DYN_PWR[1:0] 11 Enable dynamic (Class W) power saving Table 32 Low Power Headphone Playback SNR OPTIMISED MODE Headphone playback optimised for best Signal to Noise Ratio (SNR) can be enabled, resulting in a slight increase in power consumption. The register settings listed in Table 33 can be added at the start of the power up sequence in order to implement this mode. The LOUT1VOL and ROUT1VOL settings may require adjustment due to the additional attenuation of HPL_VOL[2:0] and HPR_VOL[2:0]. To partly offset the increase in power consumption due to selecting “SNR Optimised mode”, it is recommended to select Dynamic (Classs W) power saving) using CP_DYN_PWR=11. This saves power but only slightly impacts THD + noise performance. REGISTER ADDRESS BITS LABEL SETTING DESCRIPTION R30 (1Eh) Clocking 3 0 MANUAL_MODE 0 Automatic configuration of system clock dividers. Excludes master mode audio interface clocks. R6 (06h) ADC & DAC Control 2 0 DAC_OSR128 1 Automatically configure DACDIV[2:0] for 128OSR mode. This will give a SNR improvement at the expense of power R71 (47h) Analogue HP 2 8:6 HPL_VOL[2:0] 000 Secondary HPL PGA Volume -7dB 5:3 HPR_VOL[2:0] 000 Secondary HPR PGA Volume -7dB 2:0 HP_BIAS_BOOST[2:0] 000 Boost bias into headphone driver x2 R68 (44h) Analogue PGA Bias 2:0 HP_PGAS_BIAS[2:0] 000 Headphone PGA bias x 2 R82 (52h) Charge Pump B 1:0 CP_DYN_PWR[1:0] 11 Enable dynamic (Class W) power saving Table 33 Low Power Headphone Playback |
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