WM8961 datasheet(77/116 Pages) WOLFSON

77 / 116 page

WM8961

Pre-Production

PP, August 2009, Rev 3.1

ADDITIONAL SAMPLE RATE CONFIGURATION REQUIREMENTS

The DEEMPH[1:0], R5[2:1], should be configured to match the chosen DAC sample rate.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R5 (05h)

ADC and DAC

Control 1

2:1

DEEMPH[1:0]

DAC De-emphasis Filter Control

00: no de-emphasis

01: De-emphasis for 32kHz sample rate

10: De-emphasis for 44.1kHz sample rate

11: De-emphasis for 48kHz sample rate

Table 58 Additional Clock Configuration Register

DC SERVO CLOCK

The DC Servo requires to be clocked at a nominal 1.536MHz. It is controlled by the CLK_DCS_CLK

configuration bits as shown in Table 59

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R56 (38h) Clocking 4

8:5

CLK_DCS_DIV[3:0]

1000

Clock divider control for DC Servo, set to get 1.5Mhz

from SYSCLK

0000 : SYSCLK/1

0001 : SYSCLK/1.5

0010 : SYSCLK/2

0011 : Reserved

0100 : SYSCLK/3

0101 : SYSCLK/4

0110 : SYSCLK/5.5

0111 : SYSCLK/6

1000 : SYSCLK/8 (default for 12.288MHz/8 =

1.536MHz)

1001-1111 : Reserved

Table 59 DC Servo Clock Configuration

CLASS D CLOCK

The Class D clock is divided from SYSCLK.

When SYSCLK is 12.288 MHz, the Class D clock operates at an optimum frequency of 384 kHz

When SYSCLK is 11.2896 MHz, the Class D clock operates at an optimum frequency of 352.8 kHz

It is controlled using the DCLKDIV[2:0] configuration bits. For optimal operation, DCLKDIV[2:0] should

be set to divide SYSCLK by 16, giving a clock of 768 KHz. This is further divided by 2 by the Class D

function which runs at 384 KHz

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R8 (08h) Clocking2

8:6

DCLKDIV[2:0]

111

Divide of Class D clock from SYSCLK

000 : 1

001 : 2

010 : 3

011 : 4

100 : 6

101 : 8

110 : 12

111 : 16 (default for 12.288MHz/16 = 768

KHz)

(Note that Class D function further divides

by 2 to run at 384 KHz)

Table 60 Class D Clock Rate Configuration

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