WM8961 datasheet(50/116 Pages) WOLFSON

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WM8961

Pre-Production

PP, August 2009, Rev 3.1

To prevent pop noise, CLASSD_ACGAIN should not be modified while the speaker outputs are

enabled.

To avoid clipping at speaker supply, SPKVDD1 and SPKVDD2 must be high enough to support the

peak output voltage when using CLASSD_ACGAIN functions.

The maximum RMS output voltage is defined by the equation:

MAX. RMS OUTPUT VOLTAGE = AVDD/1.8* CLASSD_ACGAIN.

The above formula assumes there is 0.5dB loss (6%) due to PCB tracking. 0.5dB corresponds to 0.5

total tracking impedance with an 8

Ω speaker. If the tracking impedance is greater than or less than

6% of the speaker impedance, the output voltage will differ slightly to the above formula.

CLASS D SPEAKER OUTPUT DRIVER

The class D speaker outputs SPK_LN/SPK_LP and SPK_RN/SPK_RP can drive 1W into 8

Ω BTL

speakers at SPKVDD=5v. The Class D output stage is shown in Figure 22.

SPK_LP

SPK_LN

SPKVDD1

SPKGND1

From Left Speaker PGA

Volume Control

Left Speaker Class D

Driver Output Stage

R51,

CLASSD_ACGAIN[2:0]

R49, SPKL_ENA

SPK_RP

SPK_RN

SPKVDD2

SPKGND2

From Right Speaker PGA

Volume Control

Right Speaker Class D

Driver Output Stage

R51,

CLASSD_ACGAIN[2:0]

R49, SPKR_ENA

Figure 22 Class D Speaker Output Stage

Class D outputs reduce power consumption and maximise efficiency by reducing power dissipated in

the output drivers, delivering most of the power directly to the load. This is achieved by pulse width

modulation (PWM) of a high frequency square wave, allowing the audio signal level to be set by

controlling the pulse width. The frequency of the output waveform is controlled by DCLKDIV, and is

derived from SYSCLK.

The speaker output enable bits SPKR_ENA and SPKL_ENA should not be enabled until there is a

valid switching clock to drive the Class D outputs. This means that SYSCLK must be active, and

DCLKDIV set to an appropriate value to produce a Class D clock which runs at a nominal frequency of

384kHz when SYSCLK=12.288 MHz, or 352.8kHz when SYSCLK=11.2896MHz. This clock should

not be altered or disabled while the Class D outputs are enabled.

WM8961 Datasheet(PDF) 50 Page - Wolfson Microelectronics plc

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