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WM8961 Datasheet(PDF) 88 Page - Wolfson Microelectronics plc |
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WM8961 Datasheet(HTML) 88 Page - Wolfson Microelectronics plc |
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88 / 116 page ![]() WM8961 Pre-Production w PP, August 2009, Rev 3.1 88 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R11 (0Bh) Right DAC volume 8 DACVU 0 DAC digital volume update Writing 1 to this bit will cause left and right DAC volumes to be updated (LDACVOL and RDACVOL) 7:0 RDACVOL[7:0] 1111_1111 Right DAC digital volume FFh -> C0h : 0dB BFh : -0.375dB Beh: -0.75dB ….. in steps of -0.375dB to 02h: -71.25dB 01h: -71.625dB 00h: Digital Mute Register 0Bh Right DAC volume REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R14 (0Eh) Audio Interface 2 8:0 LRCLK_RATE[8:0] 0_0100_0000 Integer divide of BCLK. 50:50 LRCLK duty cycle is only guaranteed with even values (4, 6, … … , 510). 0_0000_0000 to 0_0000_0011 : reserved 0_0000_0100 : 4 … 0_0100_0000 : 64 … 1_1111_1110 : 510 1_1111_1111: Reserved Register 0Eh Audio Interface 2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R15 (0Fh) Software Reset 15:0 SW_RST_DEV_ID1[15:0] 0001_1000_0000_0001 Software Reset Register 0Fh Software Reset |
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