WM8961 datasheet(78/116 Pages) WOLFSON

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WM8961

Pre-Production

PP, August 2009, Rev 3.1

CHARGE PUMP CLOCK

The Charge pump is driven from the SYSCLK plus a 4 kHz clock also generated from the SYSCLK,

and requires a minimum SYSCLK of 2.8224 MHz. The charge pump internal clock is derived from

SYSCLK, using a clock divider to generate a nominal 1MHz clock, as shown in Figure 43. The clock

divider ratio depends on the SAMPLE_RATE[2:0] and CLK_SYS_RATE[3:0] register settings.

For example, with MCLKDIV=0, SAMPLE_RATE[2:0]=000:

256fs: CLK_SYS_RATE[3:0]=0011 gives a charge pump clock division ratio of 12, hence

•

MCLK=12.288MHz gives a charge pump frequency of 1.024MHz at full output power.

•

MCLK=11.2896MHz gives a charge pump frequency of 940.8kHz at full output power.

128fs: CLK_SYS_RATE[3:0]=0001 gives a charge pump clock division ratio of 6, hence

•

MCLK=6.144MHz gives a charge pump frequency of 1.024MHz at full output power.

•

MCLK=5.6448MHz gives a charge pump frequency of 940.8kHz at full output power

TIMEOUT CLOCK

The timeout clock triggers a volume update if a zero-cross has not been detected within the

configured time-frame. The timeout is enabled by TOEN and the timeout period is controlled by the

CLK_TO_DIV register as shown in Table 61

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R30 (1Eh) Clocking 3

8:7

CLK_TO_DIV[1:0]

Timeout/slow clock divider setting

00 : 125Hz ( timeout = 8ms)

01 : 250Hz ( timeout = 4ms)

10 : 500Hz ( timeout = 2ms)

11 : 1kHz ( timeout = 1ms)

R23 (17h) Additional

control(1)

TOEN

Slow clock enable for volume update timeout

Table 61 Volume Update Timeout Control

VMID GENERATOR

An internal VMID generator generates AVDD/2 as a reference voltage to be used as the virtual ground

for most internal analogue signal processing circuits. The internal VMID is output on the VMID pin.

This pin requires a 4.7uF filtering capacitor.

VMIDSEL is the enable for the VMID reference, which defaults to disabled. VMIDSEL allows the

charging and discharging of the external VMID capacitor to be controlled. It is recommended that the

user use the fast start-up mode (VMIDSEL=11) when VMID is initially enabled. Then the user should

switch to a lower power operating mode (VMIDSEL=01) for normal operation.

•

Fast Start Up: use10kΩ divider

•

Normal Mode: use 100kΩ divider

•

Standby: use 500kΩ divider

WM8961 Datasheet(PDF) 78 Page - Wolfson Microelectronics plc

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