AD1843JS datasheet(41/64 Pages) AD

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AD1843

REV. 0

–41–

(C2M7:4) must be programmed to the Conversion clock rate established using Control Register Address 20 and the

C2X8/7 bit. If the actual Conversion clock differs from the value selected by C2M7:4, then the resultant Bit clock will

be different from the rate selected by the ratio of the C2M7:4 selected rate to the Control Register Address 20 plus

the C2X8/7 bit actual rate.

C2M3:0

Bit Clock Frequency*

C2M7:4

Conversion (Sample) Rate

0000

2,400

Hertz

0000

7,200

Hertz

0001

4,800

0001

8,400

0010

7,200

0010

9,000

0011

9,600

0011

9,600

0100

12,000

0100

11,200

0101

14,400

0101

12,000

0110

16,800

0110

12,800

0111

19,200

0111

7,200

× 8/7

1000

21,600

1000

9,000

× 8/7

1001

24,000

1001

9,600

× 8/7

1010

26,400

1010

12,000

× 8/7

1011

28,800

1011

Reserved

1100

Reserved

1100

Reserved

1101

Reserved

1101

Reserved

1110

Reserved

1110

Reserved

1111

See Below

1111

See Below

*Bit clock frequencies listed will be increased by 200 Hz if C2P200 is set to “1.”

When C2M7:4 is programmed to “1111” and C2M3:0 is programmed to “1111,” the Bit clock rate will be 128 times

the Conversion rate.

When in Video Lock Mode (C2REF and C2VID are both set to “1”):

Bits C2M7:0 select the Conversion clock rate. The most significant bit (C2M7) must be set to indicate the type of

video lock, either NTSC or PAL. For an NTSC lock, C2M7 must be reset to “0,” and the SYNC2 pin must receive

the NTSC sync frequency (525 lines/frame

× 30 Hz × 1000/1001 frame rate ≈ 15.734 kHz). For a PAL lock, C2M7

must be set to “1,” and the SYNC2 pin must receive the PAL sync frequency (625 lines/frame

× 25 Hz frame rate ≈

15.625 kHz). The next three most significant bits (C2M6:4) select a desired base Conversion clock rate, and the least

significant four bits (C2M3:0) select a divisor. The Conversion clock created by Clock Generator 2 will be the base

divided by the divisor. The following tables list the possible choices for base and divisor.

NTSC

(C2M7 = “0”):

Base Frequency In Hz (C2M6:4)

48,000

32,000

44,100

× 2/3

48,000*

44,056

Divisor

(C2M3:0)

(000)

(001)

(010)

(011)

(100)

(101)

(0000)

Yes

(0001)

Yes

(0010)

Yes

(0011)

Yes

(0100)

Yes

(0101)

Yes

(0110)

Yes

(0111)

Yes

*When C2M6:4 = “100,” base frequency is 48,000 Hz only if NTSC sync rate is increased by 1001/1000, or is exactly 15.750 kHz.

PAL

(C2M7 = “1”):

Base Frequency In Hz (C2M6:4)

48,000

32,000

44,100

× 2/3

Divisor

(C2M3:0)

(000)

(001)

(010)

(011)

(0000)

Yes

(0001)

Yes

(0010)

Yes

(0011)

Yes

(0100)

Yes

(0101)

Yes

(0110)

Yes

(0111)

Yes

Initial default state after reset: 0000 0000 1111 1111 (00FF hex). Cleared to default and cannot be written to when:

the RESET pin is asserted LO; or when the PWRDWN pin is asserted LO.

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