AD1843JS datasheet(35/64 Pages) AD

35 / 64 page

AD1843

REV. 0

–35–

Address 11

Output Control—DAC1 Digital Attenuation

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

LDA1AM

res

LDA1A5

LDA1A4

LDA1A3

LDA1A2

LDA1A1

LDA1A0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

RDA1AM

res

RDA1A5

RDA1A4

RDA1A3

RDA1A2

RDA1A1

RDA1A0

LDA1AM

Left DAC1 Digital Mute

0 = Left DAC1 Enabled

1 = Left DAC1 Muted

LDA1A5:0

Left DAC1 Digital Attenuation Select. Least significant bit represents –1.5 dB.

000000 = +0.0 dB Attenuation

111111 = –94.5 dB Attenuation

RDA1AM

Right DAC1 Digital Mute

0 = Right DAC1 Enabled

1 = Right DAC1 Muted

RDA1A5:0

Right DAC1 Digital Attenuation Select. Least significant bit represents –1.5 dB.

000000 = +0.0 dB Attenuation

111111 = –94.5 dB Attenuation

res

Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.

Initial default state after reset: 0000 0000 0000 0000 (0000 hex). Cleared to default and cannot be written to when:

the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; or when the PDNO bit in Control Register

Address 0 is set to “1” (all conversions disabled).

Address 12

Output Control—DAC2 Digital Attenuation

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

LDA2AM

res

LDA2A5

LDA2A4

LDA2A3

LDA2A2

LDA2A1

LDA2A0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

RDA2AM

res

RDA2A5

RDA2A4

RDA2A3

RDA2A2

RDA2A1

RDA2A0

LDA2AM

Left DAC2 Digital Mute

0 = Left DAC2 Enabled

1 = Left DAC2 Muted

LDA2A5:0

Left DAC2 Digital Attenuation Select. Least significant bit represents –1.5 dB.

000000 = +0.0 dB Attenuation

111111 = –94.5 dB Attenuation

RDA2AM

Right DAC2 Digital Mute

0 = Right DAC2 Enabled

1 = Right DAC2 Muted

RDA2A5:0

Right DAC2 Digital Attenuation Select. Least significant bit represents –1.5 dB.

000000 = +0.0 dB Attenuation

111111 = –94.5 dB Attenuation

res

Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.

Initial default state after reset: 0000 0000 0000 0000 (0000 hex). Cleared to default and cannot be written to when:

the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; or when the PDNO bit in Control Register

Address 0 is set to “1” (all conversions disabled).

AD1843JS Datasheet(PDF) 35 Page - Analog Devices

AD1843JS Datasheet(HTML) 35 Page - Analog Devices

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