AD1843JS datasheet(29/64 Pages) AD

29 / 64 page

AD1843

REV. 0

–29–

OVL1:0

ADC Left Overrange Detect. These bits record the largest output magnitude on the ADC left channel and are

cleared to “00” after any write to this register. The peak amplitude as recorded by these bits is “sticky,” i.e., the larg-

est output magnitude recorded by these bits will persist until these bits are explicitly cleared. They are also cleared by

powering down the ADC left channel (see the ADLEN bit in Control Register Address 27).

00 = Greater than –1.0 dB underrange

01 = Between –1.0 dB and 0 dB underrange

10 = Between 0 dB and 1 dB overrange

11 = Greater than 1.0 dB overrange

res

Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.

Initial default state after reset: 0000 0000 0000 0000 (0000 hex). Cleared to default when: the RESET pin is asserted

LO; when the PWRDWN pin is asserted LO; or when the PDNO bit in Control Register Address 0 is set to “1” (all

conversions disabled).

Address 2

Input Control—ADC Source and Gain/Attenuation

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

LSS2

LSS1

LSS0

LMGE

LIG3

LIG2

LIG1

LIG0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

RSS2

RSS1

RSS0

RMGE

RIG3

RIG2

RIG1

RIG0

LSS2:0

Left ADC Source Select

000 = Left Line Input

001 = Left Mic Input

010 = Left Auxiliary 1 Input

011 = Left Auxiliary 2 Input

100 = Left Auxiliary 3 Input

101 = Mono Input

110 = Left DAC1 Output

111 = Left DAC2 Output

LMGE

Left ADC Microphone Gain Enable

0 = 0 dB Gain

1 = +20 dB Gain

LIG3:0

Left ADC Input Gain. Least significant bit represents +1.5 dB.

0000 = 0.0 dB Gain

1111 = +22.5 dB Gain

RSS2:0

Right ADC Source Select

000 = Right Line Input

001 = Right Mic Input

010 = Right Auxiliary 1 Input

011 = Right Auxiliary 2 Input

100 = Right Auxiliary 3 Input

101 = Mono Input

110 = Right DAC1 Output

111 = Right DAC2 Output

RMGE

Right ADC Microphone Gain Enable

0 = 0 dB Gain

1 = +20 dB Gain

RIG3:0

Right ADC Input Gain. Least significant bit represents +1.5 dB.

0000 = 0.0 dB Gain

1111 = +22.5 dB Gain

Initial Default State after Reset: 0000 0000 0000 0000 (0000 hex). Cleared to default and cannot be written to when:

the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; or when the PDNO bit in Control Register 0

is set to “1” (all conversions disabled).

AD1843JS Datasheet(PDF) 29 Page - Analog Devices

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