AD1843JS datasheet(22/64 Pages) AD

22 / 64 page

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AD1843

SERIAL INTERFACE INPUT

Note that the references to slot numbers are valid only when the AD1843 is configured in master mode. For slave mode, bus owner-

ship does not necessarily start on Slot 0.

Control Word Input (Slot 0 or 16)

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

res

DA2V

DA1V

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

R/W

res

IA4

IA3

IA2

IA1

IA0

DA2V

DAC2 Input Valid Flag. When in DAC2 stereo mode, setting this bit to “1” indicates that slots 4 and 5

contain valid playback data for the left and right channels of DAC2, respectively. When in DAC2 mono

mode, setting this bit to “1” indicates that slot 4 contains valid playback data for both left and right channels

of DAC2. Slot 5 is ignored in DAC2 mono mode. When this bit is reset to “0,” data in slots 4 and 5 is

ignored. This bit is ignored if the AD1843 did not request data for DAC2 in the last frame (see the DA2RQ

bit in the Status Word Output).

DA1V

DAC1 Input Valid Flag. When in DAC1 stereo mode, setting this bit to “1” indicates that slots 2 and 3

contain valid playback data for the left and right channels of DAC1, respectively. When in DAC1 mono

mode, setting this bit to “1” indicates that slot 2 contains valid playback data for both left and right channels

of DAC1. Slot 3 is ignored in DAC1 mono mode. When this bit is reset to “0,” data in slots 2 and 3 is

ignored. This bit is ignored if the AD1843 did not request data for DAC1 in the last frame (see the DA1RQ

bit in the Status Word Output).

R/W

Read/Write Request. Either a read from or a write to a Control Register occurs every frame. Setting this bit

to “1” indicates a Control Register read while resetting this bit to “0” initiates a Control Register write. Bits

IA4:0 define the Control Register address. When reading, the contents of the Control Register addressed are

transmitted during slot 1 of the following frame. When writing, the data to be written is taken from slot 1

and the former contents of the Control Register are transmitted during slot 1 of the following frame.

IA4:0

Control Register address for read or write.

res

Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.

Control Register Write Data Input (Slot 1 or 17)

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

DATA15

DATA14

DATA13

DATA12

DATA11

DATA10

DATA9

DATA8

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

Format for the input data to written to the addressed Control Register. MSB is first.

DAC1 Left Sample Input (Slot 2 or 18)

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

DATA15

DATA14

DATA13

DATA12

DATA11

DATA10

DATA9

DATA8

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

Data format may be 8-bit unsigned linear PCM, 16-bit signed linear PCM, 8-bit

µ-Law companded, or 8-bit A-Law companded.

MSB is first. DATA7:0 are ignored in 8-bit linear or 8-bit companded modes.

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